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參數(shù)資料
| 型號： | M38031F5-XXXKP |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 59/119頁 |
| 文件大?。?/td> | 1575K |
| 代理商： | M38031F5-XXXKP |
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Rev.1.00
REJ03B0212-0100
Apr 2, 2007
Page 59 of 117
3803 Group (Spec.L)
A/D CONVERTER (successive approximation type)
[AD Conversion Register 1, 2 (AD1, AD2)] 0035
16
,
0038
16
The AD conversion register is a read-only register that stores the
result of an A/D conversion. When reading this register during an
A/D conversion, the previous conversion result is read.
Bit 7 of the AD conversion register 2 is the conversion mode
selection bit. When this bit is set to “0”, the A/D converter
becomes the 10-bit A/D mode. When this bit is set to “1”, that
becomes the 8-bit A/D mode. The conversion result of the 8-bit
A/D mode is stored in the AD conversion register 1. As for 10-bit
A/D mode, not only 10-bit reading but also only high-order 8-bit
reading of conversion result can be performed by selecting the
reading procedure of the AD conversion registers 1, 2 after A/D
conversion is completed (in Figure 54).
As for 10-bit A/D mode, the 8-bit reading inclined to MSB is
performed when reading the AD converter register 1 after A/D
conversion is started; and when the AD converter register 1 is
read after reading the AD converter register 2, the 8-bit reading
inclined to LSB is performed.
[AD/DA Control Register (ADCON)] 0034
16
The AD/DA control register controls the A/D conversion
process. Bits 0 to 2 and bit 4 select a specific analog input pin.
Bit 3 signals the completion of an A/D conversion. The value of
this bit remains at “0” during an A/D conversion, and changes to
“1” when an A/D conversion ends. Writing “0” to this bit starts
the A/D conversion.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AV
SS
and V
REF
into 1024, and that outputs the comparison
voltage in the 10-bit A/D mode (256 division in 8-bit A/D mode).
The A/D converter successively compares the comparison
voltage Vref in each mode, dividing the V
REF
voltage (see
below), with the input voltage.
10-bit A/D mode (10-bit reading)
REF
1024
Vref =
× n (n = 0
1023)
10-bit A/D mode (8-bit reading)
REF
256
Vref =
× n (n = 0
255)
8-bit A/D mode
Vref =
× (n
0.5) (n = 1
255)
=0
(n = 0)
Channel Selector
The channel selector selects one of ports P6
7
/AN
7
to P6
0
/AN
0
or
P0
7
/AN
15
to P0
0
/AN
8
, and inputs the voltage to the comparator.
Comparator and Control Circuit
The comparator and control circuit compares an analog input
voltage with the comparison voltage, and then stores the result in
the AD conversion registers 1, 2. When an A/D conversion is
completed, the control circuit sets the AD conversion completion
bit and the AD interrupt request bit to “1”.
Note that because the comparator consists of a capacitor
coupling, set f(X
IN)
to 500 kHz or more during an A/D
conversion.
Fig 53. Structure of AD/DA control register
Fig 54. Structure of 10-bit A/D mode reading
V
V
REF
256
V
AD/DA control register
(ADCON : address 0034
16
)
Analog input pin selection bits 1
b2 b1 b0
0 0 0: P6
0
/AN
0
0 0 1: P6
1
/AN
1
0 1 0: P6
2
/AN
2
0 1 1: P6
3
/AN
3
1 0 0: P6
4
/AN
4
1 0 1: P6
5
/AN
5
1 1 0: P6
6
/AN
6
1 1 1: P6
7
/AN
7
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
Analog input pin selection bit 2
0: AN
0
to AN
7
side
1: AN
8
to AN
15
side
Not used (returns “0” when read)
DA
1
output enable bit
0: DA
1
output disabled
1: DA
1
output enabled
DA
2
output enable bit
0: DA
2
output disabled
1: DA
2
output enabled
or
P0
0
/AN
8
or
P0
1
/AN
9
or
P0
2
/AN
10
or
P0
3
/AN
11
or
P0
4
/AN
12
or
P0
5
/AN
13
or
P0
6
/AN
14
or
P0
7
/AN
15
b7
b0
10-bit reading
(Read address 0038
16
before 0035
16
)
AD conversion register 2
(AD2: address 0038
16
)
AD conversion register 1
(AD1: address 0035
16
)
Note
:Bits 2 to 6 of address 0038
16
become “0” at reading.
8-bit reading
(Read only address 0035
16
)
AD conversion register 1
(AD1: address 0035
16
)
b9
b7
b0
b8 b7 b6 b5 b4 b3 b2
b7
0
b0
b9 b8
b7
b7
b0
b6 b5 b4 b3 b2 b1 b0
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