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參數(shù)資料
| 型號： | M38027M5 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 45/51頁 |
| 文件大?。?/td> | 692K |
| 代理商： | M38027M5 |
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MITSUBISHI MICROCOMPUTERS
3802 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
45
Note:
When f(X
IN
) = 8 MHz and bit 6 of address 001A
16
is “1”. Divide this value by four when f(X
IN
) = 8 MHz and bit 6 of address 001A
16
is “0”.
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR
0
, CNTR
1
input cycle time
CNTR
0
, CNTR
1
input “H” pulse width
INT
0
to INT
4
input “H” pulse width
CNTR
0
, CNTR
1
input “L” pulse width
INT
0
to INT
4
input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time
Serial I/O2 input set up time
Serial I/O1 input hold time
Serial I/O2 input hold time
t
w(RESET)
t
c(X
IN
)
t
wH(X
IN
)
t
wL(X
IN
)
t
c(CNTR)
t
wH(CNTR)
t
wH(INT)
t
wL(CNTR)
t
wL(INT)
t
c(S
CLK1
)
t
c(S
CLK2
)
t
wH(S
CLK1
)
t
wH(S
CLK2
)
t
wL(S
CLK1
)
t
wL(S
CLK2
)
t
su(R
X
D–S
CLK1
)
t
su(S
IN2
–S
CLK2
)
t
h(S
CLK1
–R
X
D)
t
h(S
CLK2
–S
IN2
)
Symbol
Parameter
Limits
Typ.
Min.
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
2
125
50
50
200
80
80
80
80
800
1000
370
400
370
400
220
200
100
200
Max.
SWITCHING CHARACTERISTICS 1
(Extended operating temperature version)
(V
CC
= 4.0 to 5.5 V, V
SS =
0 V, T
a
= –40 to 85
°
C, unless otherwise noted)
TIMING REQUIREMENTS 1 (Extended operating temperature version)
(V
CC
= 4.0 to 5.5 V, V
SS =
0 V, T
a
= –40 to 85
°
C, unless otherwise noted)
Serial I/O1 clock output “H” pulse width
Serial I/O2 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O2 output delay time (Note 2)
Serial I/O1 output valid time (Note 1)
Serial I/O2 output valid time (Note 2)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
140
200
30
30
30
40
30
30
Symbol
Parameter
Limits
Typ.
Min.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
t
c(S
CLK1
)/2–30
t
c(S
CLK2
)/2–160
t
c(S
CLK1
)/2–30
t
c(S
CLK2
)/2–160
–30
0
10
10
Max.
t
wH(S
CLK1
)
t
wH(S
CLK2
)
t
wL(S
CLK1
)
t
wL(S
CLK2
)
t
d(S
CLK1
–T
X
D)
t
d(S
CLK2
–S
OUT2
)
t
v(S
CLK1
–T
X
D)
t
v(S
CLK2
–S
OUT2
)
t
r(S
CLK1
)
t
f(S
CLK1
)
t
r(S
CLK2
)
t
f(S
CLK2
)
t
r(CMOS)
t
f(CMOS)
Test conditions
Fig. 36
Note1:
When the P4
5
/T
X
D P-channel output disable bit of the UART control register (bit 4 of address 001B
16
) is “0”.
2:
When the P5
1
/S
OUT2
P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D
16
) is “0”.
3:
X
OUT
pin excluded.
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