參數(shù)資料
型號(hào)： M38027M3
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 15/51頁
文件大?。?/td> 692K
代理商： M38027M3
MITSUBISHI MICROCOMPUTERS
3802 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
15
Fig. 6 Interrupt control
Fig. 7 Structure of interrupt-related registers
Interrupt disable flag (I)
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
b7 b0
b7 b0
b7 b0
b7 b0
b7 b0
Interrupt edge selection register
(INTEDGE : address 003A
16
)
INT
0
active edge selection bit
INT
1
active edge selection bit
Not used (returns “0” when read)
INT
2
active edge selection bit
INT
3
active edge selection bit
INT
4
active edge selection bit
Not used (returns “0” when read)
Interrupt request register 1
(IREQ1 : address 003C
16
)
INT
0
interrupt request bit
INT
1
interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Interrupt control register 1
(ICON1 : address 003E
16
)
INT
0
interrupt enable bit
INT
1
interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
0 : No interrupt request issued
1 : Interrupt request issued
Interrupt request register 2
(IREQ2 : address 003D
16
)
CNTR
0
interrupt request bit
CNTR
1
interrupt request bit
Serial I/O2 interrupt request bit
INT
2
interrupt request bit
INT
3
interrupt request bit
INT
4
interrupt request bit
AD converter interrupt request bit
Not used (returns “0” when read)
Interrupt control register 2
(ICON2 : address 003F
16
)
CNTR
0
interrupt enable bit
CNTR
1
interrupt enable bit
Serial I/O2 interrupt enable bit
INT
2
interrupt enable bit
INT
3
interrupt enable bit
INT
4
interrupt enable bit
AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
0 : Falling edge active
1 : Rising edge active
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