
1-17
HARDWARE
3802 GROUP USER’S MANUAL
Fig. 13 Port block diagram (single-chip mode) (2)
(14) Port P6
(13) Port P5
6
(12) Ports P5
4
, 5
5
(9) Port P5
1
(10) Port P5
2
(11) Port P5
3
Serial I/O2 transmit end signal
Serial I/O2 port selection bit
P5
1
/S
OUT2
P-channel output disable bit
Direction register
Data bus
Port latch
Serial I/O2 output
Serial I/O2 external clock input
Serial I/O2
synchronous clock selection bit
Serial I/O2 port selection bit
Direction register
Data bus
Port latch
Serial I/O2 clock output
Direction register
Data bus
Port latch
Serial I/O2 ready output
S
RDY2
output enable bit
Direction register
Data bus
Port latch
Pulse output mode
Timer output
CNTR
0
, CNTR
1
Interrupt input
Direction register
Data bus
Port latch
PWM output
PWM output enable bit
A-D conversion input
Analog input pin selection bit
Direction register
Data bus
Port latch
FUNCTIONAL DESCRIPTION