參數(shù)資料
型號： M38023E3
廠商： Mitsubishi Electric Corporation
英文描述： SWITCH SPDT 5A PIN PLUNGER PCB
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 38/51頁
文件大?。?/td> 692K
代理商： M38023E3
MITSUBISHI MICROCOMPUTERS
3802 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
38
Note:
When f(X
IN
) = 8 MHz and bit 6 of address 001A
16
is “1”. Divide this value by four when f(X
IN
) = 8 MHz and bit 6 of address 001A
16
is “0”.
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR
0
, CNTR
1
input cycle time
CNTR
0
, CNTR
1
input “H” pulse width
INT
0
to INT
4
input “H” pulse width
CNTR
0
, CNTR
1
input “L” pulse width
INT
0
to INT
4
input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time
Serial I/O2 input set up time
Serial I/O1 input hold time
Serial I/O2 input hold time
t
w(RESET)
t
c(X
IN
)
t
wH(X
IN
)
t
wL(X
IN
)
t
c(CNTR)
t
wH(CNTR)
t
wH(INT)
t
wL(CNTR)
t
wL(INT)
t
c(S
CLK1
)
t
c(S
CLK2
)
t
wH(S
CLK1
)
t
wH(S
CLK2
)
t
wL(S
CLK1
)
t
wL(S
CLK2
)
t
su(R
X
D–S
CLK1
)
t
su(S
IN2
–S
CLK2
)
t
h(S
CLK1
–R
X
D)
t
h(S
CLK2
–S
IN2
)
Symbol
Parameter
Limits
Typ.
Min.
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
TIMING REQUIREMENTS 1
(V
CC
= 4.0 to 5.5 V, V
SS =
0 V, T
a
= –20 to 85
°
C, unless otherwise noted)
2
125
50
50
200
80
80
80
80
800
1000
370
400
370
400
220
200
100
200
Max.
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR
0
, CNTR
1
input cycle time
CNTR
0
, CNTR
1
input “H” pulse width
INT
0
to INT
4
input “H” pulse width
CNTR
0
, CNTR
1
input “L” pulse width
INT
0
to INT
4
input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time
Serial I/O2 input set up time
Serial I/O1 input hold time
Serial I/O2 input hold time
t
w(RESET)
t
c(X
IN
)
t
wH(X
IN
)
t
wL(X
IN
)
t
c(CNTR)
t
wH(CNTR)
t
wH(INT)
t
wL(CNTR)
t
wL(INT)
t
c(S
CLK1
)
t
c(S
CLK2
)
t
wH(S
CLK1
)
t
wH(S
CLK2
)
t
wL(S
CLK1
)
t
wL(S
CLK2
)
t
su(R
X
D–S
CLK1
)
t
su(S
IN2
–S
CLK2
)
t
h(S
CLK1
–R
X
D)
t
h(S
CLK2
–S
IN2
)
Symbol
Parameter
Limits
Typ.
Min.
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
TIMING REQUIREMENTS 2
(V
CC
= 3.0 to 5.5 V, V
SS =
0 V, T
a
= –20 to 85
°
C, unless otherwise noted)
2
500/
(3 V
CC
–8)
200/
(3 V
CC
–8)
200/
(3 V
CC
–8)
500
230
230
230
230
2000
2000
950
950
950
950
400
400
200
300
Max.
Note:
When f(X
IN
) = 2 MHz and bit 6 of address 001A
16
is “1”. Divide this value by four when f(X
IN
) = 2 MHz and bit 6 of address 001A
16
is “0”.
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