![](http://datasheet.mmic.net.cn/280000/M38023M1D512SP_datasheet_16084972/M38023M1D512SP_169.png)
3802 GROUP USER’S MANUAL
3-43
APPENDIX
3.5 List of registers
Fig. 3.5.19 Structure of D-A 1 conversion, D-A 2 conversion register
Fig. 3.5.20 Structure of Interrupt edge selection register
D-A1 conversion register, D-A2 conversion register
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
D-A1 conversion register (DA1), D-A2 conversion register (DA2)
[Address : 36
16
, 37
16
]
An output value of each D-A converter is set.
W
R
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
1
2
3
0
0
0
0
Interrupt edge selection register (INTEDGE) [Address : 3A
16
]
Name
4
5
6
7
0
0
0
0
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
INT
0
interrupt edge
selection bit
INT
1
interrupt edge
selection bit
Nothing is allocated for this bit. This is a write
disabled bit.When this bit is read out, the value is “0.”
INT
2
interrupt edge
selection bit
INT
3
interrupt edge
selection bit
INT
4
interrupt edge
selection bit
Nothing is allocated for these bits. These are write disabled
bits. When these bits are read out, the values are “0.”