參數(shù)資料
型號： M38004E8SP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDIP64
封裝： 0.750 INCH, 1.78 MM PITCH, PLASTIC, SDIP-64
文件頁數(shù)： 10/174頁
文件大?。?/td> 1752K
代理商： M38004E8SP
3800 GROUP USER’S MANUAL
APPENDIX
3.1 Electrical characteristics
3-4
Note: When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”.
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT5 input “H” pulse width
INT0 to INT5 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
tW(RESET)
tc(XIN)
tWH(XIN)
tWL(XIN)
tc(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tc(SCLK)
tWH(SCLK)
tWL(SCLK)
tsu(RXD–SCLK)
th(SCLK–RXD)
Symbol
Parameter
Limits
Min.
s
ns
Unit
Table 3.1.4 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85
°C, unless otherwise noted)
3.1.4 Timing requirements and Switching characteristics
2
125
50
200
80
800
370
220
100
Typ.
Max.
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT5 input “H” pulse width
INT0 to INT5 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
Symbol
Parameter
Limits
Min.
s
ns
Unit
Table 3.1.5 Timing requirements (2) (VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –20 to 85
°C, unless otherwise noted)
2
500/
(3 VCC–8)
200/
(3 VCC–8)
200/
(3 VCC–8)
500
230
2000
950
400
200
Typ.
Max.
Note: When bit 6 of address 001A16 is “1” (clock synchronous mode). Divide this value by four when bit 6 of address 001A16 is “0” (UART
mode).
tW(RESET)
tc(XIN)
tWH(XIN)
tWL(XIN)
tc(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tc(SCLK)
tWH(SCLK)
tWL(SCLK)
tsu(RXD–SCLK)
th(SCLK–RXD)
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