參數(shù)資料
型號(hào)： M37920S4CGP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 20 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù)： 10/39頁
文件大?。?/td> 438K
代理商： M37920S4CGP
M37920S4CGP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
18
DC ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 20 MHz, unless otherwise noted)
Parameter
High-level output voltage A0–A23, CS0, D0–D7,
D8/P20–D15/P27, P30,
P40–P44, P50–P57,
P60–P66, P70–P73,
P80–P86, P91–P93,
P120–P122
High-level output voltage A0–A23, CS0, D0–D7,
D8/P20–D15/P27, P40,
P44, P91–P93
High-level output voltage RD, BLW, BHW/P33,
P94/CAS/W, P95/WRL/LCAS,
P96/WRH/UCAS
Low-level output voltage A0–A23, CS0, D0–D7,
D8/P20–D15/P27, P30,
P40–P44, P50–P57,
P60–P66, P70–P73,
P80–P86, P91–P93,
P120–P122
Low-level output voltage A0–A23, CS0, D0–D7,
D8/P20–D15/P27, P40,
P44, P91–P93
Low-level output voltage RD, BLW, BHW/P33,
P94/CAS/W, P95/WRL/LCAS,
P96/WRH/UCAS
Hysteresis TA0IN–TA4IN, TB0IN–TB2IN,
INT0–INT4, DMAREQ0–DMAREQ3,
ADTRG, CTS0, CLK0, CLK1,
NMI, RDY, HOLD, RxD0, RxD1
Hysteresis RESET
Hysteresis XIN
High-level input current D0–D7, D8/P20–D15/P27,
P30, P33, P40–P44,
P50–P57, P60–P66,
P70–P73, P80–P86,
P91–P96, P120–P122,
XIN, RESET, BYTE,
MD0, MD1, NMI
Low-level input current D0–D7, D8/P20–D15/P27,
P30, P33, P40–P44,
P50–P57, P60–P66,
P70–P73, P80–P86,
P91–P96, P120–P122,
XIN, RESET, BYTE,
MD0, MD1, NMI
RAM hold voltage
Power source current
Unit
V
A
V
mA
A
f(XIN) = 20 MHz.
Ta = 25 °C when
clock is stopped.
Ta = 80 °C when
clock is stopped.
Test conditions
IOH = –10 mA
IOH = –400
A
IOH = –10 mA
IOH = –400
A
IOL = 10 mA
IOL = 2 mA
IOL = 10 mA
IOL = 2 mA
VI = 5.0 V
VI = 0 V
When clock is stoped.
Symbol
VOH
VOL
VT+ —VT–
IIH
IIL
VRAM
ICC
Min.
3
4.7
3.4
4.8
0.4
0.5
0.1
2
Limits
Typ.
25
Max.
2
0.45
1.6
0.4
1
1.5
0.3
5
–5
50
1
20
At reset in micro-
processor mode,
output-only pins
are open, and the
other pins are con-
nected to Vss.
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