參數(shù)資料
型號(hào): M37902FGCHP
廠商: Mitsubishi Electric Corporation
英文描述: DIODE SCHOTTKY DUAL COMMON-ANODE 25V 150mW 0.32V-vf 200mA-IFM 1mA-IF 2uA-IR SOT-523 3K/REEL
中文描述: 單片16位CMOS微機(jī)
文件頁(yè)數(shù): 56/143頁(yè)
文件大?。?/td> 1463K
代理商: M37902FGCHP
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M37902FCCHP, M37902FGCHP, M37902FJCHP
56
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
nored. (See Figure 50.) Note that bits 5, 6, and 7 of the up-down reg-
ister (address 44
16
) are the two-phase pulse signal processing se-
lect bits for timers A2, A3 and A4 respectively. Each timer operates
in normal event counter mode when the corresponding bit is
0
and
performs two-phase pulse signal processing when it is
1
.
Count is started by setting the count start bit to
1
. Data write and
read are performed in the same way as for normal event counter
mode. Note that the direction register of the input port must be set to
input mode because two kinds of pulse signals, described above,
are input. Also, there can be no pulse output in this mode.
Data write and data read are performed in the same way as for timer
mode. That is, when data is written to timer Ai halted, it is also writ-
ten to the reload register and the counter. When data is written to
timer Ai which is busy, the data is written to the reload register, but
not to the counter. The counter is reloaded with new data from the
reload register at the next reload time. The counter can be read at
any time.
In event counter mode, whether to increment or decrement the
counter can also be determined by supplying two kinds of pulses of
which phases differ by 90
°
to timer A2, A3, or A4. There are two types
of two-phase pulse processing operations. One uses timers A2 and
A3, and the other uses timer A4. In both processing operations, two
pulses described above are input to the TA
jOUT
(j = 2 to 4) pin and
TAj
IN
pin respectively.
When timers A2 and A3 are used, as shown in Figure 48, the count
is incremented when a rising edge is input to the TAk
IN
pin after the
level of TAk
OUT
(k=2, 3) pin changes from
L
to
H
, and when the
falling edge is input, the count is decremented.
For timer A4, as shown in Figure 49, when a phase-related pulse
with a rising edge input to the TA4
IN
pin is input after the level of
TA4
OUT
pin changes from
L
to
H
, the count is incremented at the
respective rising edge and falling edge of the TA4
OUT
pin and TA4
IN
pin.
When a phase-related pulse with a falling edge input to the TA4
OUT
pin is input after the level of TA4
IN
pin changes from
H
to
L
, the
count is decremented at the respective rising edge and falling edge
of the TA4
IN
pin and TA4
OUT
pin. When performing this two-phase
pulse signal processing, timer Aj mode register bit 0 and bit 4 must
be set to
1
and bits 1, 2, 3, and 5 must be
0
. Bits 6 and 7 are ig-
Fig. 50 Bit configuration of timer Aj mode register when performing
two-phase pulse signal processing in event counter mode
Fig. 48 Two-phase pulse processing operation of timers A2 and A3
Fig. 49 Two-phase pulse processing operation of timer A4
7 6 5 4 3 2 1 0
1
0
×
×
1
0
0
0
0 1 : Always
01
in event counter mode
0 1 0 0 : Always
0100
when processing
two-phase pulse signal
×
×
: Not used in event counter mode
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Addresses
58
16
59
16
5A
16
TAk
OUT
TAk
IN
(k = 2, 3)
Increment-
count
Increment-
count
Increment-
count
Decrement-
count
Decrement-
count
Decrement-
count
TA4
OUT
TA4
IN
Decrement-count at each edge
Increment-count at each edge
Decrement-count at each edge
Increment-count at each edge
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