參數(shù)資料
型號(hào)： M37736EHB
廠商： Mitsubishi Electric Corporation
英文描述： PROM VERSION OF M37736EHBXXXGP
中文描述： PROM的版本M37736EHBXXXGP
文件頁數(shù)： 5/96頁
文件大小： 1328K
代理商： M37736EHB
5
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BASIC FUNCTION BLOCKS
The M37736MHBXXXGP contains the following peripheral devices
on a single chip: ROM, RAM, CPU, bus interface unit, timers, serial
I/O, A-D converter, I/O ports, clock generating circuit and others. Each
of these devices is described below.
MEMORY
The memory map is shown in Figure 1. The address space has a
capacity of 16 Mbytes and is allocated to addresses from 0
16
to
FFFFFF
16
. The address space is divided by 64-Kbyte unit called bank.
The banks are numbered from 0
16
to FF
16
. However, in the external
bus mode B, banks 10
16
to FF
16
cannot be accessed.
Built-in ROM, RAM and control registers for internal peripheral devices
are assigned to banks 0
16
and 1
16
.
The 124-Kbyte area from addresses 1000
16
to 1FFFF
16
is the built-in
ROM. Addresses FFD6
16
to FFFF
16
are the RESET and interrupt
vector addresses and contain the interrupt vectors. Refer to the section
on interrupts for details.
The 3968-byte area allocated to addresses from 80
16
to FFF
16
is the
built-in RAM. In addition to storing data, the RAM is used as stack
during a subroutine call or interrupts.
Peripheral devices such as I/O ports, A-D converter, serial I/O, timer,
and interrupt control registers are allocated to addresses from 0
16
to
7F
16
.
Additionally, the internal ROM and RAM area can be modified by
software. Refer to the section on ROM area modification function for
details.
A 256-byte direct page area can be allocated anywhere in bank 0
16
by using the direct page register (DPR). In the direct page addressing
mode, the memory in the direct page area can be accessed with two
words. Hence program steps can be reduced.
Fig. 1 Memory map
A-D/UART2 trans./rece.
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT
2
/Key input
INT
0
Watchdog timer
DBC
BRK instruction
Zero divide
RESET
Internal peripheral
devices
control registers
refer to Fig. 2 for
detail information
Interrupt vector table
000000
16
00FFFF
16
010000
16
01FFFF
16
Bank 0
16
Bank 1
16
FE0000
16
FEFFFF
16
FF0000
16
FFFFFF
16
Bank FF
16
Bank FE
16
01FFFF
16
00FFD6
16
000FFF
16
001000
16
000000
16
00007F
16
000080
16
Internal RAM
3968 bytes
Internal ROM
124 Kbytes
00FFFE
16
00FFD6
16
00007F
16
000000
16
UART1 transmission
UART1 receive
UART0 transmission
UART0 receive
INT
1
00FFFF
16
Notes 1.
Internal ROM and RAM area can be modified. (Refer to the section on ROM area modification function.)
2.
In the external bus mode B, banks 10
16
to FF
16
cannot be accessed.
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