參數(shù)資料
型號(hào)： M37549G3-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO24
封裝： 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件頁數(shù)： 38/84頁
文件大?。?/td> 1378K
代理商： M37549G3-XXXFP
Rev.2.02
Mar 31, 2009
Page 43 of 81
REJ03B0202-0202
7549 Group
Fig 55. Block diagram of watchdog timer
Notes
(1) The watchdog timer operates in wait mode. To prevent
underflow, write to the watchdog timer control register.
The watchdog timer stops in stop mode, but starts counting
at the same time as exiting stop mode. After exiting stop
mode, it continues counting during oscillation stabilization
time. To prevent underflow during the period, the watchdog
timer H count source selection bit (bit 7) in the watchdog
timer control register (address 003916) should be set to “0”
before executing the STP instruction.
Note that the watchdog timer continues counting even if the
STP instruction is executed in the following two conditions:
1 Stopping the low-speed on-chip oscillator: Disabled (bit
4 in FSROM2)
Source clock of the watchdog timer: Low-speed on-chip
oscillator/16 (bit 0 in FSROM2)
2 Stopping the low-speed on-chip oscillator: Disabled (bit
4 in FSROM2)
Source clock of the watchdog timer:
φSOURCE (bit 0 in
FSROM2)
φSOURCE: Low-speed on-chip oscillator (bits 5 and 4 in
CLKM)
(2) STP instruction function selection bit
The function of the STP instruction can be selected by the
bit 2 in FSROM2. This bit cannot be used for rewriting by
executing the STP instruction.
When this bit is set to “0”, stop mode is entered by
executing the STP instruction.
When this bit is set to “1”, internal reset occurs by
executing the STP instruction.
Watchdog timer H (8)
Data bus
Watchdog timer L (8)
“FF16” is set at
WDTCON writing
1/16
φSOURCE
Low-speed on-chip
oscillator
Watchdog timer source
clock selection bit
(bit 0 of FSROM2)
Watchdog timer disable bit
(bit 1 of FSROM2)
Reset
circuit
Internal reset
STP instruction function
selection bit
(bit 3 of FSROM2)
STP Instruction
Reset pin input
Watchdog timer H
count source selection bit
(bit 7 of WDTCON)
Watchdog timer H count source
initial value selection bit
(bit 2 of FSROM2)
FSROM2: Function set ROM data 2
WDTCON: Watchdog timer control register
CPUM: CPU mode register
“FF16” is set at
WDTCON writing
Initial value setting
after releasing reset
“0”
“1”
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