參數(shù)資料
型號(hào)： M37547G4-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO36
封裝： 8.40 X 15 MM, 0.80 MM PITCH, PLASTIC, SSOP-36
文件頁(yè)數(shù)： 54/97頁(yè)
文件大小： 1064K
代理商： M37547G4-XXXFP
REJ03B0156-0122
Rev.1.22
Mar 31, 2009
page 58 of 94
7547 Group
● On-chip oscillation division ratio
At on-chip oscillator mode, division ratio of on-chip oscillator for
CPU clock is selected by setting value of on-chip oscillation divi-
sion ratio selection register. The division ratio of on-chip oscillation
for CPU clock is selected from among 1/1, 1/2, 1/8, 1/128. The op-
eration clock for the peripheral function block is not changed by
setting value of this register.
■ Notes on On-chip Oscillation Division Ratio
When system is released from reset, ROSC/8 (on-chip oscillator
middle-speed mode) is selected for CPU clock.
When state transition from the ceramic or RC oscillation to on-
chip oscillator, ROSC/8 (on-chip oscillator middle-speed mode)
is selected for CPU clock.
When the MCU operates by on-chip oscillator for the main clock
without external oscillation circuit, connect XIN pin to VCC
through a resistor and leave XOUT pin open.
Set “10010x002” (x = 0 or 1) to CPUM.
Fig. 75 Structure of on-chip oscillation division ratio selection register
On-chip oscillation division ratio selection register
(RODR: address 003716, initial value: 0216)
On-chip oscillator division ratio
b1 b0
0 0: On-chip oscillator double-speed mode (ROSC/1)
0 1: On-chip oscillator high-speed mode (ROSC/2)
1 0: On-chip oscillator middle-speed mode (ROSC/8)
1 1: On-chip oscillator low-speed mode (ROSC/128)
Not used (returns “0” when read)
b7
b0
Clock division ratio, XIN oscillation control, on-chip oscillator control
The state transition shown in Fig. 78 can be performed by setting
the clock division ratio selection bits (bits 7 and 6), XIN oscillation
control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of
CPU mode register. Be careful of notes on use in Fig. 78.
Count source (Timer 1, Timer A, Timer B, Timer X, Serial I/O, Serial
I/O2, A/D converter, Watchdog timer)
The count sources of these functions are affected by the clock divi-
sion selection bit of the CPU mode register.
The f(XIN) clock is supplied to the watchdog timer when selecting
f(XIN) as the CPU clock.
The on-chip oscillator output is supplied to these functions when se-
lecting the on-chip oscillator output as the CPU clock.
However, the watchdog timer is also affected by the function set
ROM.
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