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  • 參數(shù)資料
    型號(hào): M37545G1KP
    元件分類: 微控制器/微處理器
    英文描述: 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO32
    封裝: 11 X 5.60 MM, 0.65 MM PITCH, PLASTIC, LSSOP-32
    文件頁數(shù): 55/63頁
    文件大小: 774K
    代理商: M37545G1KP
    Rev.1.07
    Mar 19, 2009
    Page 59 of 60
    REJ03B0140-0107
    7545 Group
    Notes on Timers
    1. When n (0 to 255) is written to a timer latch, the frequency
    division ratio is 1/(n+1).
    2. Timer count source
    Stop timer 2, timer 3 counting to change its count source.
    3. Timer 1, timer 2, timer 3 count start timing and count time
    when operation starts
    Time to first underflow is different from time among next
    underflow by the timing to start the timer and count source
    operations after count starts.
    4. Timer 2, timer 3, carrier wave generating circuit
    The timing adjustment of the output waveform causes the
    gap between the timer count value and the output
    waveform, and the output waveform changes in the reload
    cycle after the timer underflow.
    Moreover, the timer interrupt occurs at the change point of
    the output waveform.
    (The timing of the interrupt occurrence is behind a half
    cycle of the count source, compared with timer 1.)
    Notes on Watchdog Timer
    1. The watchdog timer is operating during the wait mode.
    Write data to the watchdog timer control register to prevent
    timer underflow.
    2. The watchdog timer stops during the stop mode. However,
    the watchdog timer is running during the oscillation stabi-
    lizing time after the STP instruction is released. In order to
    avoid the underflow of the watchdog timer, the watchdog
    timer H count source selection bit (bit 7 of watchdog timer
    control register (address 3916)) must be set to “0” just
    before executing the STP instruction.
    Notes on RESET Pin
    (1) Connecting capacitor
    In case where the RESET signal rise time is long, connect a
    ceramic capacitor or others across the RESET pin and the Vss
    pin.
    And use a 1000 pF or more capacitor for high frequency use.
    When connecting the capacitor, note the following:
    Make the length of the wiring which is connected to a
    capacitor as short as possible.
    Be sure to verify the operation of application products on the
    user side.
    <Reason>
    If the several nanosecond or several ten nanosecond impulse
    noise enters the RESET pin, it may cause a microcomputer
    failure.
    Notes on Power-on Reset Circuit
    Reset occurs by the power-on reset circuit under the following
    conditions;
    when the power source voltage rises from 0 V to 1.8 V within
    1 ms.
    Also, note that reset may not occur under the following
    conditions;
    when the power source voltage rises from the voltage higher
    than 0 V.
    when it takes longer than 1 ms that the power source voltage
    rises from 0 V to 1.8 V.
    Note on Voltage Drop Detection Circuit
    The voltage drop detection circuit detection voltage of this
    product is set up lower than the minimum value of the supply
    voltage of the recommended operating conditions.
    When the supply voltage of a microcomputer falls below to the
    minimum value of recommended operating conditions and
    regoes up (ex. battery exchange of an application product),
    depending on the capacity value of the bypass capacitor added to
    the power supply pin, the following case may cause program
    failure;
    supply voltage does not fall below to VDET, and its voltage re-
    goes up with no reset.
    In such a case, please design a system which supply voltage is
    once reduced below to VDET and re-goes up after that.
    Fig 6.
    VCC and VDET
    Notes on Clock Generating Circuit
    (1) CPU mode register
    Processor mode bits (bits 1 and 0) of CPU mode register (address
    3B16) is used to control operation modes of the microcomputer.
    In order to prevent the dead-lock by erroneously writing (ex.
    program run-away), these bits can be rewritten only once after
    releasing reset.
    After rewriting, it is disabled to write any data to the bit. (The
    emulator MCU “M37545RLSS” is excluded.)
    Also, when the read-modify-write instructions (SEB, CLB, etc.)
    are executed to bits 2, 6, 7, bits 1 and 0 are locked.
    (2) Ceramic resonator
    When the ceramic resonator/quartz-crystal oscillation is used for
    the main clock, connect the ceramic resonator and the external
    circuit to pins XIN and XOUT at the shortest distance. A feedback
    resistor is built-in.
    Vcc
    VDET
    Reset
    Normal operation
    No reset
    Program failure may occur.
    Recommended
    operating condition
    min. value
    Vcc
    VDET
    Recommended
    operating condition
    min. value
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