參數(shù)資料
型號(hào)： M37544G2ASP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32
封裝： 28 X 8.90 MM, 1.78 MM PITCH, PLASTIC, SDIP-32
文件頁(yè)數(shù)： 31/77頁(yè)
文件大小： 641K
代理商： M37544G2ASP
7544 Group (QzROM version)
REJ03B0108-0103
Rev.1.03
Mar 31, 2009
page 35 of 72
A/D Converter
The functional blocks of the A/D converter are described below.
[A/D conversion register] AD
The A/D conversion register is a read-only register that stores the
result of A/D conversion. Do not read out this register during an A/
D conversion.
[A/D control register] ADCON
The A/D control register controls the A/D converter. Bit 2 to 0 are
analog input pin selection bits. Bit 4 is the AD conversion comple-
tion bit. The value of this bit remains at “0” during A/D conversion,
and changes to “1” at completion of A/D conversion.
A/D conversion is started by setting this bit to “0”.
[Comparison voltage generator]
The comparison voltage generator divides the voltage between
AVSS and VREF by 256, and outputs the divided voltages.
[Channel selector]
The channel selector selects one of ports P25/AN5 to P20/AN0,
and inputs the voltage to the comparator.
[Comparator and control circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores its result into the A/D
conversion register. When A/D conversion is completed, the con-
trol circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”. Because the comparator is constructed
linked to a capacitor, set f(XIN) to 500 kHz or more during A/D con-
version.
Fig. 34 Structure of A/D control register
Fig. 35 Block diagram of A/D converter
b7
b0
Analog input pin selection bits
A/D control register
(ADCON : address 003416, initial value: 1016)
Disable (returns “0” when read)
1 : Conversion completed
0 : Conversion in progress
AD conversion completion bit
Disable (returns “0” when read)
111 : Disable
110 : Disable
101 : P25/AN5
100 : P24/AN4
011 : P23/AN3
010 : P22/AN2
001 : P21/AN1
000 : P20/AN0
A/D control register
(Address 003416)
Channel
selector
A/D control circuit
Resistor ladder
VREF
Comparator
A/D interrupt request
b7
b0
Data bus
3
10
P20/AN0
P21/AN1
P22/AN2
P23/AN3
P24/AN4
P25/AN5
(Address 003516)
VSS
A/D conversion register (low-order)
■ Notes on A/D converter
The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that f(XIN) is 500 kHz or more during A/D conversion.
As for AD translation accuracy, on the following operating condi-
tions, accuracy may become low.
(1) Since the analog circuit inside a microcomputer becomes sen-
sitive to noise when VREF voltage is set up lower than Vcc
voltage, accuracy may become low rather than the case
where VREF voltage and Vcc voltage are set up to the same
value..
(2) When VREF voltage is lower than [ 3.0 V ], the accuracy at the
low temperature may become extremely low compared with
that at room temperature. When the system would be used at
low temperature, the use at VREF=3.0 V or more is recom-
mended.
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