參數(shù)資料
型號： M37542F4SP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP32
封裝： 8.9 X 28 MM, 1.78 MM PITCH, PLASTIC, SDIP-32
文件頁數(shù)： 98/122頁
文件大?。?/td> 1311K
代理商： M37542F4SP
7542 Group
Rev.3.03
Jul 11, 2008
Page 77 of 117
REJ03B0006-0303
■ Notes on CPU Rewrite Mode
Take the notes described below when rewriting the flash memory
in CPU rewrite mode.
●Operation speed
During CPU rewrite mode, set the system clock φ to 4.0 MHz or
less using the clock division ratio selection bits (bits 6 and 7 of ad-
dress 003B16).
●Instructions inhibited against use
The instructions which refer to the internal data of the flash
memory cannot be used during CPU rewrite mode.
●Interrupts inhibited against use
The interrupts cannot be used during CPU rewrite mode because
they refer to the internal data of the flash memory.
●Watchdog timer
If the watchdog timer has been already activated, internal reset
due to an underflow will not occur because the watchdog timer is
surely cleared during program or erase.
●Reset
Reset is always valid. The MCU is activated using the boot mode
at release of reset in the condition of CNVss = “H”, so that the pro-
gram will begin at the address which is stored in addresses
FFFC16 and FFFD16 of the boot ROM area.
Fig. 101 CPU rewrite mode set/release flowchart
End
Start
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing “1” and then “0” in succession) (Note 3)
Single-chip mode or Boot mode
Set CPU mode register (Note 1)
Using software command executes erase,
program, or other operation
Jump to control program transferred to internal RAM
(Subsequent operations are executed by control
program in this RAM)
Transfer CPU rewrite mode control program to
internal RAM
Notes1: Set the main clock as follows depending on the clock division ratio selection bits of
Write “0” to CPU rewrite mode select bit
Set CPU rewrite mode select bit to “1”
(by writing “0” and then “1” in succession)
CPU mode register (bits 6, 7 of address 003B16).
2: As for setting of these bits, refer to Table 10.
3: Before exiting the CPU rewrite mode after completing erase or program operation,
Set all user block E/W enable bit
Set 8KB user block E/W mode enable bit
(for setting to “1”, by writing “0” and then “1”
in succession)
(Note 2)
Set all user block E/W enable bit to “0”
Set 8KB user block E/W mode enable bit to “0”
always be sure to execute the read array command or reset the flash memory.
Figure 101 shows a flowchart for setting/releasing CPU rewrite mode.
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