![](http://datasheet.mmic.net.cn/30000/M37540E8FP_datasheet_2359848/M37540E8FP_302.png)
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APPENDIX
7540 Group User’s Manual
(2) Notes when selecting UART
When the clock asynchronous serial I/O1 (UART) is used, serial I/O2 can be used only when BRG
output divided by 16 is selected as the synchronous clock.
When the transmit operation is stopped, clear the transmit enable bit to “0” (transmit disabled).
q Reason
Same as (1) .
When the receive operation is stopped, clear the receive enable bit to “0” (receive disabled).
When the transmit/receive operation is stopped, clear the transmit enable bit to “0” (transmit
disabled) and receive enable bit to “0” (receive disabled).
Setup of a serial I/O1 synchronous clock selection bit when a clock asynchronous (UART) serial
I/O is selected;
“0”: P12 pin can be used as a normal I/O pin.
“1”: P12 pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it is P13 pin. It can be used as a normal I/O pin.
(3) Notes common to clock synchronous serial I/O and UART
When data transmission is executed at the state that an external clock input is selected as the
synchronous clock, set “1” to the transmit enable bit while the SCLK1 is “H” state. Also, write to the
transmit buffer register while the SCLK1 is “H” state.
When the transmit interrupt is used, set as the following sequence.
Serial I/O1 transmit interrupt enable bit is set to “0” (disabled).
Serial I/O1 transmit enable bit is set to “1”.
Serial I/O1 transmit interrupt request bit is set to “0”.
Serial I/O1 transmit interrupt enable bit is set to “1” (enabled).
q Reason
When the transmit enable bit is set to “1”, the transmit buffer empty flag and transmit shift
completion flag are set to “1”.
Accordingly, even if the timing when any of the above flags is set to “1” is selected for the transmit
interrupt source, interrupt request occurs and the transmit interrupt request bit is set.
Write to the baud rate generator (BRG) while the transmit/receive operation is stopped.
Fig. 3.3.1 Sequence of setting serial I/O1 control
register again
Set the serial I/O control register again after
the transmission and the reception circuits
are reset by clearing both the transmit enable
bit and the receive enable bit to “0.”
The transmit shift completion flag changes
from “1” to “0” with a delay of 0.5 to 1.5
shift clocks. When data transmission is
controlled with referring to the flag after
writing the data to the transmit buffer register,
note the delay.
Can be set
with the LDM
instruction at
the same time
Clear both the transmit enable bit (TE)
and the receive enable bit (RE) to “0”
Set the bits 0 to 3 and bit 6 of the
serial I/O1 control register
Set both the transmit enable bit (TE)
and the receive enable bit (RE), or one
of them to “1”
→
3.3 Notes on use