參數(shù)資料
型號： M37540M4-XXXSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP32
封裝： 0.400 INCH, 1.78 MM PITCH, PLASTIC, SDIP-32
文件頁數(shù)： 77/88頁
文件大?。?/td> 872K
代理商： M37540M4-XXXSP
7540 Group
Rev.4.00
Jun 21, 2004
page 79 of 82
REJ03B0011-0400Z
Switching characteristics measurement circuit diagram (Gen-
eral purpose)
/ / /
Measured
output pin
CMOS output
100 pF
Switching Characteristics (Extended operating temperature 125 °C version)
Table 38 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
tC(SCLK1)/2–30
–30
tC(SCLK2)/2–30
0
Min.Typ.
Max.
Symbol
Parameter
Limits
Unit
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tWH(SCLK2)
tWL(SCLK2)
td(SCLK2–SDATA2)
tv(SCLK2–SDATA2)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
Serial I/O1 output valid time
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
Note 1: Pin XOUT is excluded.
Table 39 Switching characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
Min.Typ.
Max.
Symbol
Parameter
Limits
Unit
350
50
350
50
Note 1: Pin XOUT is excluded.
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tWH(SCLK2)
tWL(SCLK2)
td(SCLK2–SDATA2)
tv(SCLK2–SDATA2)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
Serial I/O1 output valid time
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
tC(SCLK1)/2–50
–30
tC(SCLK2)/2–50
0
20
ns
10
140
30
140
30
ns
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