![](http://datasheet.mmic.net.cn/30000/M37540E8FP_datasheet_2359848/M37540E8FP_73.png)
HARDWARE
1-54
7540 Group User’s Manual
FUNCTIONAL
DESCRIPTION
SUPPLEMENT
Interrupt
7540 group permits interrupts on the 14 sources
for 42-pin version, 13 sources for 36-pin version
and 12 sources for 32-pin version. It is vector
interrupts with a fixed priority system. Accordingly,
when two or more interrupt requests occur during
the same sampling, the higher-priority interrupt is
accepted first. This priority is determined by
hardware, but variety of priority processing can be
performed by software, using an interrupt enable
bit and an interrupt disable flag.
For interrupt sources, vector addresses and interrupt
priority, refer to “Table 8.”
Table 8 Interrupt sources, vector addresses and interrupt priority
FUNCTIONAL DESCRIPTION SUPPLEMENT
Vector addresses (Note 1)
High-order
Priority
Low-order
Interrupt request generating conditions
Remarks
Interrupt source
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
Note 1: Vector addressed contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3: It is an interrupt which can use only for 36 pin version.
Non-maskable
Valid only when serial I/O1 is selected
Valid only when serial I/O1 is
selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (valid at falling)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
STP release timer underflow
Non-maskable software interrupt
At reset input
At completion of serial I/O1 data receive
At completion of serial I/O1 transmit shift or
when transmit buffer is empty
At detection of either rising or falling edge of
INT0 input
At detection of either rising or falling edge of
INT1 input
At falling of conjunction of input logical level
for port P0 (at input)
At detection of either rising or falling edge of
CNTR0 input
At detection of either rising or falling edge of
CNTR1 input
At timer X underflow
At timer Y underflow
At timer Z underflow
At timer A underflow
At completion of transmit/receive shift
At completion of A-D conversion
At timer 1 underflow
Not available
At BRK instruction execution
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Reset (Note 2)
Serial I/O1 receive
Serial I/O1 transmit
INT0
INT1 (Note 3)
Key-on wake-up
CNTR0
CNTR1
Timer X
Timer Y
Timer Z
Timer A
Serial I/O2
A-D conversion
Timer 1
Reserved area
BRK instruction