參數(shù)資料
型號: M37540M2-XXXSP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP32
封裝: 0.400 INCH, 1.78 MM PITCH, PLASTIC, SDIP-32
文件頁數(shù): 33/88頁
文件大小: 872K
代理商: M37540M2-XXXSP
7540 Group
Rev.4.00
Jun 21, 2004
page 39 of 82
REJ03B0011-0400Z
Serial I/O2 operation
By writing to the serial I/O2 register (address 003116) the serial I/
O2 counter is set to “7”.
After writing, the SDATA2 pin outputs data every time the transfer
clock shifts from “H” to “L”. And, as the transfer clock shifts from
“L” to “H”, the SDATA2 pin reads data, and at the same time the
contents of the serial I/O2 register are shifted by 1 bit.
When the internal clock is selected as the transfer clock source,
the following operations execute as the transfer clock counts up to
8.
Serial I/O2 counter is cleared to “0”.
Transfer clock stops at an “H” level.
Interrupt request bit is set.
Shift completion flag is set.
Also, the SDATA2 pin is in a high impedance state after the data
transfer is completed (refer to Fig.37).
When the external clock is selected as the transfer clock source,
the interrupt request bit is set as the transfer clock counts up to 8,
but external control of the clock is required since it does not stop.
Notice that the SDATA2 pin is not in a high impedance state on the
completion of data transfer.
Also, after the receive operation is completed, the transmit/receive
shift completion flag is cleared by reading the serial I/O2 register.
At transmit, the transmit/receive shift completion flag is cleared
and the transmit operation is started by writing to serial I/O2 regis-
ter.
Fig. 37 Serial I/O2 timing (LSB first)
D0
Note :
Synchronous clock
Serial I/O2 register
write signal
Transfer clock
(Note)
SDATA2 at serial I/O2
input receive
SDATA2 at serial I/O2
output transmit
Serial I/O2 interrupt request bit set
Transmit/receive shift completion flag set
D1
D2
D3
D4
D5
D6
D7
When the internal clock is selected as the transfer and the direction register of P1 3/SDATA2 pin is set to the input mode,
the SDATA2 pin is in a high impedance state after the data transfer is completed.
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