參數(shù)資料
型號(hào): M37540E8FP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP32
封裝: 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁數(shù): 18/88頁
文件大小: 872K
代理商: M37540E8FP
7540 Group
Rev.4.00
Jun 21, 2004
page 25 of 82
REJ03B0011-0400Z
(4) Pulse width measurement mode
In the pulse width measurement mode, the pulse width of the sig-
nal input to P14/CNTR0 pin is measured.
The operation of Timer X can be controlled by the level of the sig-
nal input from the CNTR0 pin.
When the CNTR0 active edge switch bit is “0”, the signal selected
by the timer X count source selection bit is counted while the input
signal level of CNTR0 pin is “H”. The count is stopped while the
pin is “L”. Also, when the CNTR0 active edge switch bit is “1”, the
signal selected by the timer X count source selection bit is
counted while the input signal level of CNTR0 pin is “L”. The count
is stopped while the pin is “H”.
Timer X can stop counting by setting “1” to the timer X count stop
bit in any mode.
Also, when Timer X underflows, the timer X interrupt request bit is
set to “1”.
Note on Timer X is described below;
s Note on Timer X
CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at
the falling edge of CNTR0 pin input signal. When this bit is “1”, the
CNTR0 interrupt request bit is set to “1” at the rising edge of
CNTR0 pin input signal.
Fig. 23 Structure of timer X mode register
Fig. 24 Timer count source set register
Timer X mode register
(TXM : address 002B 16, initial value: 0016)
CNTR0 active edge switch bit
0 : Interrupt at falling edge
Count at rising edge
(in event counter mode)
1 : Interrupt at rising edge
Count at falling edge
(in event counter mode)
Timer X operating mode bits
b1 b0
0
0 : Timer mode
0
1 : Pulse output mode
1
0 : Event counter mode
1
1 : Pulse width measurement mode
Not used (return “0” when read)
Timer X count stop bit
0 : Count start
1 : Count stop
b7
b0
P03/TXOUT output valid bit
0 : Output invalid (I/O port)
1 : Output valid (Inverted CNTR 0 output)
Timer count source set register
(TCSS : address 002E16, initial value: 0016)
b7
b0
Timer X count source selection bits
b1 b0
0
0 : f(XIN)/16
0
1 : f(XIN)/2
1
0 : f(XIN) (Note 1)
1
1 : Not available
Timer Y count source selection bits
b3 b2
0
0 : f(XIN)/16
0
1 : f(XIN)/2
1
0 : On-chip oscillator output (Note 2)
1
1 : Not available
Timer Z count source selection bits
b5 b4
0
0 : f(XIN)/16
0
1 : f(XIN)/2
1
0 : Timer Y underflow
1
1 : Not available
Fix this bit to “0”.
Not used (return “0” when read)
Notes 1: f(XIN) can be used as timer X count source when using
a ceramic resonator or on-chip oscillator.
Do not use it at RC oscillation.
2: System operates using an on-chip oscillator as a count source
by setting the on-cihp oscillator to oscillation enabled by bit 3
of CPUM.
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