參數(shù)資料
型號(hào): M37531M4-XXXGP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP32
封裝: 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁(yè)數(shù): 33/216頁(yè)
文件大?。?/td> 1400K
代理商: M37531M4-XXXGP
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5
5-11
INTERRUPT CONTROLLER (ICU)
32182 Group User’s Manual (Rev.1.0)
5.3 Interrupt Request Sources in Internal Peripheral I/O
The Interrupt Controller receives as inputs the interrupt requests from MJT (multijunction timer), DMAC, serial I/O,
A-D converter, RTD and CAN. For details about these interrupts, see each section in which the relevant internal
peripheral I/O is described.
Table 5.3.1 Interrupt Request Sources in Internal Peripheral I/O
Interrupt Request Sources
Contents
Number of
ICU Type of Input
Input Sources
Source ( Note 1)
TIN3–6 input interrupt request
TIN3 input
1
Level-recognized
TIN20–29 input interrupt request
TIN20–TIN23 inputs
4
Level-recognized
TIN12–19 input interrupt request
TIN16–TIN19 inputs
4
Level-recognized
TIN0–2 input interrupt request
TIN0 input
1
Level-recognized
TMS0,1 output interrupt request
TMS0, TMS1 output
2
Level-recognized
TOP8,9 output interrupt request
TOP8, TOP9 output
2
Level-recognized
TOP10 output interrupt request
TOP10 output
1
Edge-recognized
TIO4–7 output interrupt request
TIO4–TIO7 outputs
4
Level-recognized
TIO8,9 output interrupt request
TIO8, TIO9 outputs
2
Level-recognized
TOP0–5 output interrupt request
TOP0–TOP5 outputs
6
Level-recognized
TOP6,7 output interrupt request
TOP6–TOP7 outputs
2
Level-recognized
TIO0–3 output interrupt request
TIO0–TIO3 outputs
4
Level-recognized
DMA0-4 interrupt request
DMA0–4 transfer completed
5
Level-recognized
SIO1 receive interrupt request
SIO1 reception-completed or receive error interrupt
1
Edge-recognized
SIO1 transmit interrupt request
SIO1 transmission-completed or transmit buffer empty
1
Edge-recognized
interrupt
SIO0 receive interrupt request
SIO0 reception-completed or receive error interrupt
1
Edge-recognized
SIO0 transmit interrupt request
SIO0 transmission-completed or transmit buffer empty
1
Edge-recognized
interrupt
A-D0 conversion interrupt request
A-D0 converter’s scan mode one-shot operation,
1
Edge-recognized
single mode or comparate mode completed
DMA5–9 interrupt request
DMA5–9 transfer completed
5
Level-recognized
SIO2,3 transmit/receive interrupt
SIO2,3 reception-completed or receive error interrupt,
4
Level-recognized
request
transmission-completed or transmit buffer empty interrupt
RTD interrupt request
RTD interrupt generation command
1
Edge-recognized
CAN0 transmit/receive & error
CAN0 transmission or reception completed, CAN0 error
35
Level-recognized
interrupt request
passive, CAN0 error bus-off, CAN0 bus error, single shot
CAN1 transmit/receive & error
CAN1 transmission or reception completed, CAN1 error
35
Level-recognized
interrupt request
passive, CAN1 error bus-off, CAN1 bus error, single shot
Note 1: ICU type of input source
Edge-recognized: Interrupt requests are generated on a falling edge of the interrupt signal supplied to the ICU.
Level-recognized: Interrupt requests are generated when the interrupt signal supplied to the ICU is held low. For
this type of interrupt, the ICU’s Interrupt Control Register IRQ bit cannot be set or cleared in software.
5.3 Interrupt Request Sources in Internal Peripheral I/O
相關(guān)PDF資料
PDF描述
M37531M4T-XXXGP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP32
M37531M8-XXXFP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO36
M37531M4T-XXXFP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO36
M37531M4T-XXXGP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP32
M37531E4V-XXXGP 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP32
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