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參數(shù)資料
| 型號： | M37531E4V-XXXGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP32 |
| 封裝： | 7 X 7 MM, PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 144/215頁 |
| 文件大?。?/td> | 1365K |
| 代理商： | M37531E4V-XXXGP |
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HARDWARE
7531 Group User’s Manual
1-20
Interrupts
Interrupts occur by 12 different sources : 4 external sources, 7 inter-
nal sources and 1 software source.
Interrupt control
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit, and they are controlled by the
interrupt disable flag. When the interrupt enable bit and the interrupt
request bit are set to “1” and the interrupt disable flag is set to “0”, an
interrupt is accepted.
The interrupt request bit can be cleared by program but not be set.
The interrupt enable bit can be set and cleared by program.
It becomes usable by switching CNTR0 and AD conversion interrupt
sources with bit 7 of the interrupt edge selection register, timer 2 and
serial I/O2 interrupt sources with bit 6, timer X and key-on wake-up
interrupt sources with bit 5, and serial I/O1 transmit and INT1 inter-
rupt sources with bit 4.
The reset and BRK instruction interrupt can never be disabled with
any flag or bit. All interrupts except these are disabled when the in-
terrupt disable flag is set.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status regis-
ter are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. Concurrently with the push operation, the interrupt destination
address is read from the vector table into the program counter.
Notes on use
When the active edge of an external interrupt (INT0, INT1,CNTR0) is
set, the interrupt request bit may be set.
Therefore, please take following sequence:
1. Disable the external interrupt which is selected.
2. Change the active edge in interrupt edge selection register. (in
case of CNTR0: Timer X mode register)
3. Clear the set interrupt request bit to “0”.
4. Enable the external interrupt which is selected.
Table 6 Interrupt vector address and priority
Vector addresses (Note 1)
High-order
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
Priority
1
2
3
4
5
6
7
8
9
Low-order
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
Interrupt request generating conditions
At reset input
At completion of serial I/O1 data receive
At completion of serial I/O1 transmit shift or
when transmit buffer is empty
At detection of either rising or falling edge
of INT1 input
At detection of either rising or falling edge
of INT0 input
At timer X underflow
At falling of conjunction of input logical
level for port P0 (at input)
At timer 1 underflow
At timer 2 underflow
At completion of transmit/receive shift
At detection of either rising or falling edge
of CNTR0 input
At completion of A-D conversion
At BRK instruction execution
Remarks
Non-maskable
Valid when serial I/O1 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (valid at falling)
STP release timer underflow
External interrupt (active edge
selectable)
Non-maskable software interrupt
Interrupt source
Reset (Note 2)
Serial I/O1
receive
Serial I/O1
transmit
INT1 (Note 3)
INT0
Timer X
Key-on wake-up
Timer 1
Timer 2
Serial I/O2
CNTR0
A-D conversion
BRK instruction
Note 1: Vector addressed contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3: It is an interrupt which can use only for 36 pin version.
FUNCTIONAL DESCRIPTION
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