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參數(shù)資料
| 型號(hào)： | M37531E4V-XXXGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP32 |
| 封裝： | 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32 |
| 文件頁(yè)數(shù)： | 130/216頁(yè) |
| 文件大?。?/td> | 1400K |
| 代理商： | M37531E4V-XXXGP |
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9
9-2
DMAC
32182 Group User’s Manual (Rev.1.0)
9.1 Outline of the DMAC
The microcomputer internally contains a 10-channel DMAC (Direct Memory Access Controller). It allows data to
be transferred at high speed between internal peripheral I/Os, between internal RAM and internal peripheral I/O, or
between internal RAMs, as initiated by a software trigger or requested from an internal peripheral I/O.
Table 9.1.1 Outline of the DMAC
Item
Description
Number of channels
10 channels
Transfer request sources Software trigger
Request from internal peripheral I/Os: A-D converter, multijunction timer, serial I/O (reception
completed, transmit buffer empty) or CAN
DMA channels can be cascaded (Note 1)
Maximum number of
65,536 times
times transferred
Transferable address
64 Kbytes (address space from H’0080 0000 to H’0080 FFFF)
space
Transfers between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and
between internal RAMs are supported.
Transfer data size
16 or 8 bits
Transfer method
Single transfer DMA (control of the internal bus is relinquished for each transfer performed), dual-
address transfer
Transfer mode
Single transfer mode
Direction of transfer
One of three modes can be selected for the source and destination:
Address fixed
Address incremental
Ring buffered
Channel priority
DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5 > DMA6 > DMA7 > DMA8 > DMA9
(Priority is fixed)
Maximum transfer rate
13.3 Mbytes per second (when internal peripheral clock BCLK = 20 MHz)
Interrupt request
Group interrupt request can be generated when each transfer count register underflows.
Transfer area
64 Kbytes from H’0080 0000 to H’0080 FFFF (Note 2)
Note 1: The DMA channels can be cascaded in the manner described below.
Start DMA transfer on DMA1 upon completion of one DMA transfer on DMA0
Start DMA transfer on DMA5 upon completion of all DMA transfers on DMA0 (upon underflow of the transfer count
register)
Start DMA transfer on DMA2 upon completion of one DMA transfer on DMA1
Start DMA transfer on DMA0 upon completion of one DMA transfer on DMA2
Start DMA transfer on DMA3 upon completion of one DMA transfer on DMA2
Start DMA transfer on DMA4 upon completion of one DMA transfer on DMA3
Start DMA transfer on DMA6 upon completion of one DMA transfer on DMA5
Start DMA transfer on DMA7 upon completion of one DMA transfer on DMA6
Start DMA transfer on DMA5 upon completion of one DMA transfer on DMA7
Start DMA transfer on DMA8 upon completion of one DMA transfer on DMA7
Start DMA transfer on DMA9 upon completion of one DMA transfer on DMA8
Note 2: Address space from H'0081 0000 to H'0081 3FFF cannot be transferred into the internal RAM area.
9.1 Outline of the DMAC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M37531M4T-XXXSP | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP32 |
| M37531M4V-XXXGP | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP32 |
| M37531E8FP | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDSO36 |
| M37531E4GP | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP32 |
| M37531E8SP | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDIP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37531E8FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37531E8SP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37531M4 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37531M4-606SP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37531M4-680FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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