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| 型號： | M37481MXT |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 32/97頁 |
| 文件大?。?/td> | 1076K |
| 代理商： | M37481MXT |
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MITSUBISHI MICROCOMPUTERS
7480/7481 GROUP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
32
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Each of the transmit and receive registers has a buffer register
(the same address on memory). Since the shift register cannot be
written to or read from directly, transmit data is written to the trans-
mit buffer register and receive data is read from the receive buffer
register. These buffer registers can also hold the next data to be
transmitted and receive 2-byte receive data in succession.
(2) Asynchronous Serial I/O (UART) Mode
The UART mode can be selected by clearing the serial I/O mode
selection bit of the serial I/O control register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats to be used by a transmitter and a receiver must be identi-
cal.
Fig. 30 Block diagram of UART serial I/O
Fig. 31 Operation of UART serial I/O function
Receive buffer register
Clock control circuit
Serial I/O control register
Baud rate generator
Serial I/O status register
1/4
1/4
Transmit shift register shift completion flag (TSC)
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Frequency division ratio 1/(n+1)
P1
4
Receive enable bit (RE)
P1
5
P1
6
Receive shift register
Transmit shift register
Transmit buffer register
T
X
D
CLK
X
IN
R
X
D
Address 00E0
16
Address 00E2
16
Address 00E0
16
Address 00E1
16
Address 00E4
16
7-bit
1/16
1/16
UART control register
Address 00E3
16
ST/SP/PA generation
Serial I/O synchronous clock
selection bit (SCS)
OE
SP detection
8-bit
PE
FE
ST detection
Transmit enable bit (TE)
Character length
selection bit (CHAS)
Character length
selection bit
(CHAS)
BRG count source
selection bit (CSS)
Data bus
Data bus
Serial I/O enable bit (SIOE)
Serial I/O synchronous clock selection bit (SCS)
source selection bit (TIC)
ST
D
0
D
1
SP
ST
D
0
D
1
SP
Transmit or receive clock
Transmit buffer register
write signal
Serial output TxD
Receive buffer register
read signal
Serial input RxD
TBE=0
TSC=0
TBE=0
TBE=1
RBF=0
RBF=1
RBF=1
TSC=1
1 start bit
7/8 data bit
1/2 stop bit
ST
D
0
D
1
SP
ST
D
1
SP
*
8
Generated at 2nd bit in 2
stop bit mode
Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit during reception).
2 : The transmit interrupt (TI) can be selected to be generated when either TBE=1 or TSC=1, depending on the setting of
the transmit interrupt source selection bit of the serial I/O control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
D
0
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