參數(shù)資料
型號: M37280MFH-XXXSP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP64
封裝: 0.750 INCH, PLASTIC, SDIP-64
文件頁數(shù): 145/171頁
文件大小: 1465K
代理商: M37280MFH-XXXSP
75
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37280MFH–XXXSP, M37280MKH–XXXSP
M37280EKSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
The display position in the vertical direction is determined by count-
ing the horizontal sync signal (HSYNC). At this time, when VSYNC and
HSYNC are positive polarity (negative polarity), it starts to count the
rising edge (falling edge) of HSYNC signal from after fixed cycle of
rising edge (falling edge) of VSYNC signal. So interval from rising edge
(falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC
signal needs enough time (2 machine cycles or more) for avoiding
jitter. The polarity of HSYNC and VSYNC signals can select with the
I/O polarity control register (address 021716).
Fig. 8.11.9 Supplement Explanation for Display Position
When bits 0 and 1 of the I/O polarity control register
(address 021716) are set to “1” (negative polarity)
VSYNC signal input
VSYNC control
signal in
microcomputer
0.25 to 0.50 [
s]
( at f(XIN) = 8MHz)
(Note 2)
Not count
12345
Notes 1 : The vertical position is determined by counting falling edge of
HSYNC signal after rising edge of VSYNC control signal in the
microcomputer.
2: Do not generate falling edge of HSYNC signal near rising edge
of VSYNC control signal in microcomputer to avoid jitter.
3: The pulse width of VSYNC and HSYNC needs 8 machine cycles
or more.
8 machine cycles or more
8 machine cycles
or more
HSYNC
signal input
Period of counting
HSYNC signal
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相關代理商/技術參數(shù)
參數(shù)描述
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