參數(shù)資料
型號: M3727GM8-XXXSP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP42
封裝: 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42
文件頁數(shù): 96/131頁
文件大?。?/td> 1130K
代理商: M3727GM8-XXXSP
M3727GM6/M8–XXXSP/FP M37272E8SP/FP
Rev.1.00
Apr 01, 2001
page 65 of 127
REJ03B0132-0100Z
The vertical display start position is determined by counting the hori-
zontal sync signal (HSYNC). At this time, when VSYNC and HSYNC are
positive polarity (negative polarity), it starts to count the rising edge
(falling edge) of HSYNC signal from after fixed cycle of rising edge
(falling edge) of VSYNC signal. So interval from rising edge (falling
edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal
needs enough time (2 machine cycles or more) for avoiding jitter.
The polarity of HSYNC and VSYNC signals can select with the I/O po-
larity control register (address 00D816).
Fig. 8.11.6 Supplement Explanation for Display Position
When bits 0 and 1 of the I/O polarity control register
(address 00D816) are set to “1” (negative polarity)
VSYNC signal input
VSYNC control
signal in
microcomputer
0.25 to 0.50 [s]
( at f(XIN) = 8MHz)
Period of counting
HSYNC signal
(See note 2)
HSYNC
signal input
Not count
12345
Notes 1 : The vertical position is determined by counting falling edge of HSYNC
signal after rising edge of VSYNC control signal in the microcomputer.
2 : Do not generate falling edge of HSYNC signal near rising edge of
VSYNC control signal in microcomputer to avoid jitter.
3 : The pulse width of VSYNC and HSYNC needs 8 machine cycles or
more.
8 machine cycles
or more
8 machine cycles
or more
相關(guān)PDF資料
PDF描述
M3727GM8-XXXFP 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDSO42
M3727GM6-XXXFP 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDSO42
M37280MF-XXXSP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP64
M37280MK-XXXSP 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP64
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