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參數(shù)資料
| 型號： | M366S0823DTS |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | PC100 Unbuffered DIMM(168pin) SPD Specification(64Mb D-die base) |
| 中文描述： | PC100的無緩沖DIMM（168線）社民黨規(guī)范（64兆??；兀?/td> |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 67K |
| 代理商： | M366S0823DTS |
SERIAL PRESENCE DETECT
PC100 Unbuffered DIMM
Rev 0.1 Jan.
2000
M366S0424DTS-C80/C1H/C1L
Organization : 4Mx64
Composition : 4Mx16 *4
Used component part # : K4S641632D-TC80/ TC1H/ TC1L
# of rows in module : 1 row
# of banks in component : 4 banks
Feature : 1,000mil height & single sided component
Refresh : 4K/64ms
Contents ;
Byte #
Function Described
Function Supported
Hex value
Note
-80
-1H
-1L
-80
-1H
-1L
0
# of bytes written into serial memory at module manufacturer
128bytes
80h
1
Total # of bytes of SPD memory device
256bytes (2K-bit)
08h
2
Fundamental memory type
SDRAM
04h
3
# of row address on this assembly
12
0Ch
1
4
# of column address on this assembly
8
08h
1
5
# of module
rows
on this assembly
1
row
01h
6
Data width of this assembly
64 bits
40h
7
...... Data width of this assembly
-
00h
8
Voltage interface standard of this assembly
LVTTL
01h
9
SDRAM cycle time @CAS latency of 3
8ns
10ns
10ns
80h
A0h
A0h
2
10
SDRAM access time from clock @CAS latency of 3
6ns
6ns
6ns
60h
60h
60h
2
11
DIMM configuration type
Non parity
00h
12
Refresh rate & type
15.625us, support self refresh
80h
13
Primary SDRAM width
x16
10h
14
Error checking SDRAM width
None
00h
15
Minimum clock delay for back-to-back random column address
t
CCD
= 1CLK
01h
16
SDRAM device attributes : Burst lengths supported
1, 2, 4, 8 & full page
8Fh
17
SDRAM device attributes : # of
banks
on SDRAM device
4
banks
04h
18
SDRAM device attributes : CAS latency
2 & 3
06h
19
SDRAM device attributes : CS latency
0 CLK
01h
20
SDRAM device attributes : Write latency
0 CLK
01h
21
SDRAM module attributes
Non-buffered, non-registered
& redundant addressing
00h
22
SDRAM device attributes : General
+/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge
0Eh
23
SDRAM cycle time @CAS latency of 2
10ns
10ns
12ns
A0h
A0h
C0h
2
24
SDRAM access time from clock @CAS latency of 2
6ns
6ns
7ns
60h
60h
70h
2
25
SDRAM cycle time @CAS latency of 1
-
-
-
00h
00h
00h
26
SDRAM access time from clock @CAS latency of 1
-
-
-
00h
00h
00h
27
Minimum row precharge time (=t
RP
)
20ns
20ns
20ns
14h
14h
14h
28
Minimum row active to row active delay (t
RRD
)
16ns
20ns
20ns
10h
14h
14h
29
Minimum RAS to CAS delay (=t
RCD
)
20ns
20ns
20ns
14h
14h
14h
30
Minimum activate precharge time (=t
RAS
)
48ns
50ns
50ns
30h
32h
32h
31
Module
row
density
1
row
of 32MB
08h
32
Command and address signal input setup time
2ns
2ns
2ns
20h
20h
20h
33
Command and address signal input hold time
1ns
1ns
1ns
10h
10h
10h
34
Data signal input setup time
2ns
2ns
2ns
20h
20h
20h
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