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  • 參數(shù)資料
    型號(hào): M34570E8FP
    元件分類: 微控制器/微處理器
    英文描述: 4-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO36
    封裝: 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-36
    文件頁數(shù): 16/69頁
    文件大小: 780K
    代理商: M34570E8FP
    22
    MITSUBISHI MICROCOMPUTERS
    4570 Group
    SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
    Table 10 Timer control registers
    Timer control register W1
    W13
    W12
    W11
    W10
    at reset : 00002
    at RAM back-up : 00002
    0
    1
    0
    1
    0
    1
    0
    1
    R/W
    Stop (prescaler state initialized)
    Operating
    Instruction clock divided by 4
    Instruction clock divided by 8
    Prescaler output (ORCLK)
    Carrier output (CARRY)
    Stop (state retained)
    Operating
    Prescaler control bit
    Prescaler dividing ratio selection bit
    Timer 1 count source selection bit
    Timer 1 control bit
    Timer control register W2
    at reset : 00002
    at RAM back-up : state retained
    R/W
    0
    1
    Stop (state retained)
    Operating
    Port D9
    TOUT pin
    W23
    W22
    W21
    W20
    Timer 2 control bit
    Port D9/TOUT pin function selection bit
    Timer 2 count source selection bits
    0
    1
    W21
    0
    1
    Count source
    Prescaler output (ORCLK)
    Timer 1 underflow signal
    Instruction clock
    16-bit timer underflow signal
    Timer control register W3
    at reset : 00002
    at RAM back-up : state retained
    R/W
    0
    1
    0
    1
    Stop (state retained)
    Operating
    This bit has no function, but read/write is enabled.
    W33
    W32
    W31
    W30
    Timer 3 control bit
    Not used
    Timer 3 count source selection bits
    W20
    0
    1
    0
    1
    W31
    0
    1
    W30
    0
    1
    0
    1
    Count source
    Timer 2 underflow signal
    Prescaler output (ORCLK)
    f(XIN) or f(XIN)/2
    Not available
    Timer count value store register W5
    at reset : 002
    at RAM back-up : state retained
    R/W
    2-bit register. The contents of the high-order 2 bits (bits 9 and 8) of the 10-bit ROM pattern at address (D2D1D0A3A2A1A0) in page
    p specified by registers D and A is stored in this register W5 with the TABP p instruction.
    In addition, data can be transferred between the low-order 2 bits of register A and this register W5 with the TW5A or TAW5
    instruction. Data can be read/written to/from the high-order 2 bits of timer 1 with the T1AB or TAB1 instruction.
    Note: “R” represents read enabled, and “W” represents write enabled.
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