![](http://datasheet.mmic.net.cn/30000/M3455AG8-XXXFP_datasheet_2359525/M3455AG8-XXXFP_45.png)
Rev.1.02
Nov 26, 2008
REJ03B0224-0102
455A Group
(2) LCD clock control
The LCD clock is determined by the timer LC setting value and
timer LC count source.
After setting data to timer LC, timer LC starts counting by setting
count source with bit 2 of register W4 and setting bit 3 of register
W4 to “1.”
Accordingly, the frequency (F) of the LCD clock is obtained by
the following formula. Numbers ((1) to (3)) shown below the
formula correspond to numbers in
Figure 44, respectively.
When using the system clock (STCK) as timer LC count
source (W42=“1”)
When using the bit 4 of timer 3 as timer LC count source
(W42=“0”)
The frame frequency and frame period for each display method
can be obtained by the following formula:
Fig 44. LCD clock control circuit structure
(3) LCD RAM
RAM contains areas corresponding to the liquid crystal display.
When “1” is written to this LCD RAM, the display pixel
corresponding to the bit is automatically displayed.
Fig 45. LCD RAM map
F = STCK
×
(1)
(2)
(3)
[LC: 0 to 15]
LC + 1
1
2
1
F = T34
×
(1)
(2)
(3)
[LC: 0 to 15]
LC + 1
1
2
1
Frame frequency =
(Hz)
Frame frequency =
(Hz)
F: LCD clock frequency
1/n: Duty
n
F
n
Timer LC (4)
Reload register RLC (4)
(TLCA)
Register A
1/2
LCD clock
(TLCA)
W42
0
1
W43
T34
STCK
(3)
(1)
(2)
Z
X
1
8
9
10
11
12
13
14
15
COM
Y
bit
12
SEG0
SEG1
0
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM0
SEG0
SEG1
1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM1
SEG0
SEG1
2
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM2
SEG0
SEG1
3
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
COM3
13
SEG8
SEG9
0
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM0
SEG8
SEG9
1
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM1
SEG8
SEG9
2
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM2
SEG8
SEG9
3
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
COM3
14
SEG16
SEG17
0
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
COM0
SEG16
SEG17
1
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
COM1
SEG16
SEG17
2
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
COM2
SEG16
SEG17
3
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
COM3
15
SEG24
SEG25
0
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
COM0
SEG24
SEG25
1
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
COM1
SEG24
SEG25
2
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
COM2
SEG24
SEG25
3
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
COM3