參數(shù)資料
型號: M34518M2-XXXFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP32
封裝: 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁數(shù): 96/157頁
文件大小: 1783K
代理商: M34518M2-XXXFP
ML610Q411/ML610Q412/ML610Q415 User’s Manual
Chapter 3
Reset Function
3 – 2
3.2
Description of Registers
3.2.1
List of Registers
Address
Name
Symbol (Byte)
Symbol (Word)
R/W
Size
Initial value
0F001H
Reset status register
RSTAT
R/W
8
3.2.2
Reset Status Register (RSTAT)
Address: 0F001H
Access: R/W
Access size: 8 bits
Initial value: Undefined
7
6
5
4
3
2
1
0
RSTAT
WDTR
XSTR
POR
R/W
Initial value
0
x/0(*)
1
(*) Undefined on ML610Q411 and ML610Q412, “0” on ML610Q415.
RSTAT is a special function register (SFR) that indicates the causes by which the reset is generated.
At the occurrence of reset, the contents of RSTAT are not initialized, while the bit indicating the cause of the reset is
set to ”1”. When checking the reset cause using this function, perform write operation to RSTAT in advance and
initialize the contents of RSTAT to “00H”.
[Description of Bits]
POR (bit 0)
The POR bit is a flag that indicates that the power-on reset is generated. This bit is set to “1” when powered on.
POR
Description
0
Power-on reset not generated
1
Power-on reset generated
XSTR (bit 1)
The XSTR bit is a flag that indicates the generation of low-speed oscillation stop detect reset.
When low-speed
oscillation stops for the period specified by the low-speed oscillation stop detection time (TSTOP) or more, this bit is
set to “1”. Writing to the bit is invalid and returns always “0” when reading on ML610Q415.
XSTR
Description
0
Low-speed oscillation stop detect reset not occurred
1
Low-speed oscillation stop detect reset occurred
WDTR (bit 2)
The WSDTR is a flag that indicates that the watchdog timer reset is generated. This bit is set to “1” when the reset by
overflow of the watchdog timer is generated.
WDTR
Description
0
Watchdog timer reset not occurred
1
Watchdog timer reset occurred
Note:
No flag is provided that indicates the occurrence of reset by the RESET_N pin.
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