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參數(shù)資料
| 型號： | M34507M2-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, MICROCONTROLLER, PDSO24 |
| 封裝： | 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24 |
| 文件頁數(shù)： | 54/117頁 |
| 文件大小： | 937K |
| 代理商： | M34507M2-XXXFP |
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4507 Group
Rev.3.01
2005.02.04
page 39 of 111
REJ03B0107-0301
RAM BACK-UP MODE
The 4507 Group has the RAM back-up mode.
When the POF2 instruction is executed continuously after the
EPOF instruction, system enters the RAM back-up state.
The POF2 instruction is equal to the NOP instruction when the
EPOF instruction is not executed before the POF2 instruction.
As oscillation stops retaining RAM, the function of reset circuit and
states at RAM back-up mode, current dissipation can be reduced
without losing the contents of RAM.
Table 15 shows the function and states retained at RAM back-up.
Figure 37 shows the state transition.
(1) Identification of the start condition
Warm start (return from the RAM back-up state) or cold start (re-
turn from the normal reset state) can be identified by examining the
state of the power down flag (P) with the SNZP instruction.
(2) Warm start condition
When the external wakeup signal is input after the system enters
the RAM back-up state by executing the EPOF instruction and
POF2 instruction continuously, the CPU starts executing the pro-
gram from address 0 in page 0. In this case, the P flag is “1.”
(3) Cold start condition
The CPU starts executing the program from address 0 in page 0
when;
reset pulse is input to RESET pin, or
reset by watchdog timer is performed, or
In this case, the P flag is “0.”
Table 15 Functions and states retained at RAM back-up
Function
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
Port level
Selected oscillation circuit
Timer control register W1
Timer control registers W2, W6
Clock control register MR
Interrupt control registers V1, V2
Interrupt control register I1
Timer 1 function
Timer 2 function
A/D conversion function
A/D control register Q1
Pull-up control registers PU0 to PU2
Key-on wakeup control registers K0 to K2
External 0 interrupt request flag (EXF0)
Timer 1 interrupt request flag (T1F)
Timer 2 interrupt request flag (T2F)
Watchdog timer flags (WDF1)
Watchdog timer enable flag (WEF)
16-bit timer (WDT)
A/D conversion completion flag (ADF)
Interrupt enable flag (INTE)
RAM back-up
O
(Note 5)
O
O
O
(Note 3)
O
(Note 3)
(Note 4)
(Note 4)
Notes 1:“O” represents that the function can be retained, and “” repre-
sents that the function is initialized.
Registers and flags other than the above are undefined at RAM
back-up, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack register and is
initialized to “7” at RAM back-up.
3: The state of the timer is undefined.
4: Initialize the watchdog timer flag WDF1 with the WRST instruction,
and then execute the POF2 instruction.
5: As for the D2/C pin, the output latch of port C is set to “1” at the
RAM back-up. However, the output latch of port D2 is retained.
As for the other ports, their output levels are retained at the RAM
back-up.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M34507M4-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34508G4FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34508G4GP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34508G4GP#U0 | 功能描述:MCU 2/5V 4096 QZROM PB-FREE 20-S RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:720/4500 標(biāo)準(zhǔn)包裝:300 系列:78K0R/Ix3 核心處理器:78K/0R 芯體尺寸:16-位 速度:40MHz 連通性:3 線 SIO，I²C，LIN，UART/USART 外圍設(shè)備:DMA，LVD，POR，PWM，WDT 輸入/輸出數(shù):27 程序存儲(chǔ)器容量:16KB（16K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:38-SSOP 包裝:托盤 |
| M34508G4GP(#UO) | 制造商:Renesas Electronics Corporation 功能描述: |
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