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參數(shù)資料
| 型號： | M34507E4FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, MICROCONTROLLER, PDSO24 |
| 封裝： | 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24 |
| 文件頁數(shù)： | 115/117頁 |
| 文件大?。?/td> | 937K |
| 代理商： | M34507E4FP |
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–
V10 = 0: (EXF0) = 1
(INT) = “L”
However, I12 = 0
(INT) = “H”
However, I12 = 1
–
V12 = 0: (T1F) = 1
V13 = 0: (T2F) =1
Skip condition
Datailed description
Carry
flag
CY
Clears (0) to interrupt enable flag INTE, and disables the interrupt.
Sets (1) to interrupt enable flag INTE, and enables the interrupt.
When V10 = 0 : Skips the next instruction when external 0 interrupt request flag EXF0 is “1.” After skipping,
clears (0) to the EXF0 flag. When the EXF0 flag is “0,” executes the next instruction.
When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register
V1)
When I12 = 0 : Skips the next instruction when the level of INT pin is “L.” Executes the next instruction when
the level of INT pin is “H.”
When I12 = 1 : Skips the next instruction when the level of INT pin is “H.” Executes the next instruction when
the level of INT pin is “L.” (I12: bit 2 of interrupt control register I1)
Transfers the contents of interrupt control register V1 to register A.
Transfers the contents of register A to interrupt control register V1.
Transfers the contents of interrupt control register V2 to register A.
Transfers the contents of register A to interrupt control register V2.
Transfers the contents of interrupt control register I1 to register A.
Transfers the contents of register A to interrupt control register I1.
Transfers the contents of timer control register W1 to register A.
Transfers the contents of register A to timer control register W1.
Transfers the contents of timer control register W2 to register A.
Transfers the contents of register A to timer control register W2.
Transfers the contents of timer control register W6 to register A.
Transfers the contents of register A to timer control register W6.
Transfers the high-order 4 bits (T17–T14) of timer 1 to register B.
Transfers the low-order 4 bits (T13–T10) of timer 1 to register A.
Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1. Trans-
fers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1.
Transfers the high-order 4 bits (T27–T24) of timer 2 to register B.
Transfers the low-order 4 bits (T23–T20) of timer 2 to register A.
Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2. Trans-
fers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2.
Transfers the contents of register B to the high-order 4 bits (R17–R14) of reload register R1, and the con-
tents of register A to the low-order 4 bits (R13–R10) of reload register R1.
When V12 = 0 : Skips the next instruction when timer 1 interrupt request flag T1F is “1.” After skipping,
clears (0) to the T1F flag. When the T1F flag is “0,” executes the next instruction.
When V12 = 1 : This instruction is equivalent to the NOP instruction. (V12: bit 2 of interrupt control register V1)
When V13 = 0 : Skips the next instruction when timer 1 interrupt request flag T2F is “1.” After skipping,
clears (0) to the T2F flag. When the T2F flag is “0,” executes the next instruction.
When V13 = 1 : This instruction is equivalent to the NOP instruction. (V13: bit 3 of interrupt control register V1)
4507 Group
Rev.3.01
2005.02.04
page 95 of 111
REJ03B0107-0301
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