![](http://datasheet.mmic.net.cn/130000/M34506M4-XXXFP_datasheet_5008350/M34506M4-XXXFP_89.png)
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
1-76
HARDWARE
4506 Group User’s Manual
INSTRUCTIONS
TABE (Transfer data to Accumulator and register B from register E)
0000101010
02A
11
–
Grouping:
Register to register transfer
Description: Transfers the high-order 4 bits (E7–E4) of
register E to register B, and low-order 4 bits
of register E to register A.
Operation:
(B)
← (E7–E4)
(A)
← (E3–E0)
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
00100p4
p3
p2
p1
p0
0p
13
–
Grouping:
Arithmetic operation
Description: Transfers bits 7 to 4 to register B and bits 3 to
0 to register A. These bits 7 to 0 are the ROM
pattern in address (DR2 DR1 DR0 A3 A2 A1
A0)2 specified by registers A and D in page p.
Note:
p is 0 to 15 for M34506M2, and p is 0 to 31
for M34506M4/E4.
When this instruction is executed, be careful
not to over the stack because 1 stage of
stack register is used.
Operation:
(SP)
← (SP) + 1
(SK(SP))
← (PC)
(PCH)
← p
(PCL)
← (DR2–DR0, A3–A0)
(B)
← (ROM(PC))7–4
(A)
← (ROM(PC))3–0
(PC)
← (SK(SP))
(SP)
← (SP) – 1
TAD (Transfer data to Accumulator from register D)
0001010001
051
11
–
Grouping:
Register to register transfer
Description: Transfers the contents of register D to the
low-order 3 bits (A2–A0) of register A.
Note:
When this instruction is executed, “0” is
stored to the bit 3 (A3) of register A.
Operation:
(A2–A0)
← (DR2–DR0)
(A3)
← 0
8
+p
TABAD (Transfer data to Accumulator and register B from register AD)
1001111001
279
11
–
Grouping:
A-D conversion operation
Description: In the A-D conversion mode (Q13 = 0), trans-
fers the high-order 4 bits (AD9–AD6) of register
AD to register B, and the middle-order 4 bits
(AD5–AD2) of register AD to register A. In the
comparator mode (Q13 = 1), transfers the high-
order 4 bits (AD7–AD4) of comparator register
to register B, and the low-order 4 bits (AD3–
AD0) of comparator register to register A.
Operation:
In A-D conversion mode (Q13 = 0),
(B)
← (AD9–AD6)
(A)
← (AD5–AD2)
In comparator mode (Q13 = 1),
(B)
← (AD7–AD4)
(A)
← (AD3–AD0)
(Q13 : bit 3 of A-D control register Q1)
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)