參數(shù)資料
型號: M34280E1FP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDSO20
封裝: 0.300 INCH, 1.27 MM PITCH, PLASTIC, SOP-20
文件頁數(shù): 35/48頁
文件大小: 605K
代理商: M34280E1FP
Interrupt
Mitsubishi microcomputers
M16C / 62N Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
39
Interrupt source
Vector table addresses
Remarks
Address (L) to address (H)
Undefined instruction
FFFDC16 to FFFDF16
Interrupt on UND instruction
Overflow
FFFE016 to FFFE316
Interrupt on INTO instruction
BRK instruction
FFFE416 to FFFE716
If the vector contains FF16, program execution starts from
the address shown by the vector in the variable vector table
Address match
FFFE816 to FFFEB16
There is an address-matching interrupt enable bit
Single step (Note)
FFFEC16 to FFFEF16
Do not use
Watchdog timer
FFFF016 to FFFF316
________
DBC (Note)
FFFF416 to FFFF716
Do not use
NMI
FFFF816 to FFFFB16
_______
External interrupt by input to NMI pin
Reset
FFFFC16 to FFFFF16
Note: Interrupts used for debugging purposes only.
Figure 1.10.2. Format for specifying interrupt vector addresses
Mid address
Low address
0 0 0 0
High address
0 0 0 0
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
LSB
MSB
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 1.10.2 shows the format for
specifying the address.
Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and
variable vector table in which addresses can be varied by the setting.
Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 1.10.1 shows the interrupts assigned to the fixed vector
tables and addresses of vector tables.
Table 1.10.1. Interrupts assigned to the fixed vector tables and addresses of vector tables
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