4
32176 Group
Mitsubishi Microcomputers
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Under Development
Jan. 30, 2003
Rev.1.4
Table 2. Outline Performance (1/2)
Functional Block
Features
M32R CPU core
M32R family CPU core,internally configured in 32 bits
Built-in multiplier-accumulator (32 × 16 + 56)
Basic bus cycle: 25 ns (CPU clock frequency at 40 MHz, Internal peripheral clock frequency at 20 MHz)
Logical address space: 4G bytes, linear
General-purpose register: 32-bit register × 16, Control register: 32-bit register × 5
accumulator: 56 bits
External data bus
16 bits data bus
Instruction set
16-bit/32-bit instruction formats
83 instructions/9 addressing modes
Internal flash memory
M32176F4VFP/M32176F4TFP: 512K bytes
M32176F3VFP/M32176F3TFP: 384K bytes
M32176F2VFP/M32176F2TFP: 256K bytes
Rewrite durability: 100 times
Internal RAM
24K bytes
DMAC
10 channels (DMA transfers between internal peripheral I/Os, between internal peripheral I/O and internal
RAM, and between internal RAMs)
Channels can be cascaded and can operate in combination with internal peripheral I/O
Multijunction timer
37 channels of multijunction timers
16-bit output-related timers × 11 channels (single-shot, delayed single-shot)
16-bit input/output-related timers × 10 channels (event count mode, single-shot, PWM, measurement)
16-bit input-related timers × 8 channels (measurement, event count mode)
32-bit input-related timers × 8 channels (measurement)
Flexible timer configuration is possible through interconnection of channels using the event bus.
A-D converter
10-bit multifunction A-D converters
Input 16 channels
Scan-based conversion can be switched between N (N = 1-16) channels
Capable of interrupt conversion during scan
8-bit/10-bit readout function
Sample & hold function
Disconnection detector assist function
Injection current bypass circuit
Serial I/O
4 channels (The serial I/Os can be set for synchronous serial I/O or UART. SIO2, SIO3 are UART mode only)
Real-time debugger (RTD)
1-channels dedicated clock-synchronized serial
Entire area of internal RAM
Can access the internal RAM for read/rewrite from outside independently of the CPU, and also generate an
exclusive-use interrupt.
Interrupt controller
Controls interrupts from internal peripheral I/Os
(Priority can be set to one of 8 levels including interrupt disabled)
Wait controller
Controls wait when accessing external extended area
(1 to 4 wait cycles inserted + prolonged by external WAIT# signal input)
CAN
Two channels, each having 16-channel message slots
JTAG
Boundary-Scan function