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Page 57
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td(DB – WR) =
10 X m
9
– 25
[ns] (if external bus cycle is a
φ + bφ, m= (bx2)-1)
th(RD – AD) =
f(BCLK) X 2
10
9
– 10
[ns]
th(WR – AD) =
f(BCLK) X 2
10
9
– 10
[ns]
th(RD – CS) =
f(BCLK) X 2
10
9
– 10
[ns]
th(WR – CS) =
f(BCLK) X 2
10
9
– 10
[ns]
th(WR – DB) =
f(BCLK) X 2
10
9
– 10
[ns]
td(AD – ALE) =
f(BCLK) X 2
9
– 20
[ns] (if external bus cycle is a
φ + bφ, n= a)
th(ALE – AD) =
f(BCLK) X 2
9
– 10
[ns] (if external bus cycle is a
φ + bφ, n= a)
f(BCLK) X 2
1. Values can be obtained from the following equations, according to BCLK frequency.
2. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle.
3. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle.
10 X m
10 X n
4. Values can be obtained from the following equations, according to BCLK frequency and external bus cycle.
10 X n
NOTES:
5. tc ns is added when recovery cycle is inserted.
See Figure 5.2
Switching Characteristics
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.23 Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space with the multiplexed bus)