參數(shù)資料
型號(hào)： M30840MCT-XXXGP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, MROM, 32 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁(yè)數(shù)： 61/91頁(yè)
文件大小： 903K
代理商： M30840MCT-XXXGP
63
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Som
e parametric
limits
are
subject
to
change.
Table 13 Definition of each bit in status register
Status Register
The status register shows the operating status of the flash
memory and whether erase operations and programs ended suc-
cessfully or in error. It can be read in the following ways:
(1) By reading an arbitrary address from the User ROM area after
writing the read status register command (7016)
(2) By reading an arbitrary address from the User ROM area in the
period from when the program starts or erase operation starts
to when the read array command (FF16) is input.
Also, the status register can be cleared by writing the clear status
register command (5016).
After reset, the status register is set to “8016”.
Table 13 shows the status register. Each bit in this register is ex-
plained below.
Sequencer status (SR7)
The sequencer status indicates the operating status of the flash
memory. This bit is set to “0” (busy) during write or erase operation
and is set to “1” when these operations ends.
After power-on, the sequencer status is set to “1” (ready).
Erase status (SR5)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is reset to “0”.
Program status (SR4)
The program status indicates the operating status of write opera-
tion. When a write error occurs, it is set to “1”.
The program status is reset to “0” when it is cleared.
If “1” is written for any of the SR5 and SR4 bits, the read array,
program, and block erase commands are not accepted. Before ex-
ecuting these commands, execute the clear status register
command (5016) and clear the status register.
Also, if any commands are not correct, both SR5 and SR4 are set
to “1”.
Each bit of
SRD bits
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Sequencer status
Reserved
Erase status
Program status
Reserved
Status name
“1”
Ready
-
Terminated normally
-
“0”
Busy
-
Terminated normally
-
Definition
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