參數(shù)資料
型號(hào)： M3062AFCTGP-B7
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 51/87頁
文件大?。?/td> 919K
代理商： M3062AFCTGP-B7
VCC1 = VCC2 = 3V
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics (M16C/62P)
4
8
f
o
4
0
2
,
1
0
p
e
S
0
3
.
2
.
v
e
R
Z
0
3
2
0
-
1
0
B
3
0
J
E
R
page 55
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)
Table 5.32 Memory Expansion and Microprocessor Modes
Table 5.31 External Clock Input (XIN Input)
Max.
External Clock Rise Time
ns
tr
Min.
External Clock Input Cycle Time
External Clock Input HIGH Pulse Width
External Clock Input LOW Pulse Width
External Clock Fall Time
ns
tc
tw(H)
tw(L)
tf
Parameter
Symbol
Unit
Standard
100
40
18
(NOTE 1)
(NOTE 2)
(NOTE 3)
50
40
0
50
0
1. Calculated according to the BCLK frequency as follows:
Min.
Data Input Setup Time
ns
tsu(DB-RD)
tsu(RDY-BCLK )
Parameter
Symbol
Unit
Max.
Standard
ns
RDY Input Setup Time
Data Input Hold Time
ns
th(RD-DB)
th(BCLK -RDY)
ns
RDY Input Hold Time
ns
HOLD Input Setup Time
tsu(HOLD-BCLK )
ns
HOLD Input Hold Time
th(BCLK-HOLD )
Data Input Access Time (for setting with no wait)
ns
tac1(RD-DB)
ns
tac2(RD-DB)
tac3(RD-DB)
Data Input Access Time (for setting with wait)
Data Input Access Time (when accessing multiplex bus area)
f(BCLK)
– 60
0.5 X 109
[ns]
2. Calculated according to the BCLK frequency as follows:
f(BCLK)
– 60
(n–0.5) X 109
[ns]
3. Calculated according to the BCLK frequency as follows:
f(BCLK)
– 60
(n–0.5) X 109
[ns]
n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait
setting.
n is “2” for 2-wait setting, “3” for 3-wait setting.
NOTES:
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