參數(shù)資料
型號(hào)： M30627FHPGP-D5
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP128
封裝： 14 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-128
文件頁數(shù)： 38/87頁
文件大?。?/td> 919K
代理商： M30627FHPGP-D5
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics (M16C/62P)
4
8
f
o
4
0
2
,
1
0
p
e
S
0
3
.
2
.
v
e
R
Z
0
3
2
0
-
1
0
B
3
0
J
E
R
page 43
Table 5.28 Memory Expansion and Microprocessor Modes
(for 2- to 3-wait setting, external area access and multiplex bus selection)
VCC1 = VCC2 = 5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)
Symbol
Standard
Measuring
Condition
Max.
Min.
Parameter
Unit
td(BCLK-AD)
Address Output Delay Time
25
ns
th(BCLK-AD)
Address Output Hold Time (in relation to BCLK)
4
ns
td(BCLK-CS)
Chip Select Output Delay Time
25
ns
th(BCLK-CS)
Chip Select Output Hold Time (in relation to BCLK)
4
ns
th(RD-AD)
Address Output Hold Time (in relation to RD)
(NOTE 1)
td(BCLK-RD)
RD Signal Output Delay Time
25
ns
th(BCLK-RD)
RD Signal Output Hold Time
0
ns
th(WR-AD)
Address Output Hold Time (in relation to WR)
(NOTE 1)
td(BCLK-WR)
WR Signal Output Delay Time
25
ns
td(BCLK-DB)
Data Output Delay Time (in relation to BCLK)
40
ns
th(BCLK-DB)
Data Output Hold Time (in relation to BCLK)
4
ns
td(DB-WR)
Data Output Delay Time (in relation to WR)
(NOTE 2)
ns
th(BCLK-WR)
WR Signal Output Hold Time
0
ns
th(RD-CS)
Chip Select Output Hold Time (in relation to RD)
(NOTE 1)
th(WR-CS)
Chip Select Output Hold Time (in relation to WR)
(NOTE 1)
ns
th(WR-DB)
Data Output Hold Time (in relation to WR)
ns
(NOTE 1)
1. Calculated according to the BCLK frequency as follows:
f(BCLK)
0.5 X 109
[ns]
2. Calculated according to the BCLK frequency as follows:
f(BCLK)
(n–0.5) X 109
–40
[ns]
3. Calculated according to the BCLK frequency as follows:
f(BCLK)
0.5 X 109
–25
[ns]
n is “2” for 2-wait setting, “3” for 3-wait setting.
td(BCLK-ALE)
ALE Signal Output Delay Time (in relation to BCLK)
15
ns
th(BCLK-ALE)
ALE Signal Output Hold Time (in relation to BCLK)
– 4ns
th(ALE-AD)
ALE Signal Output Hold Time (in relation to Adderss)
ns
td(AD-RD)
RD Signal Output Delay From the End of Adress
ns
0
td(AD-WR)
WR Signal Output Delay From the End of Adress
ns
0
tdZ(RD-AD)
Address Output Floating Start Time
ns
8
td(AD-ALE)
ALE Signal Output Delay Time (in relation to Address)
ns
(NOTE 3)
(NOTE 4)
–10
4. Calculated according to the BCLK frequency as follows:
f(BCLK)
0.5 X 109
[ns]
–15
NOTES:
HLDA Output Delay Time
40
ns
td(BCLK-HLDA)
See Figure 5.2
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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