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參數(shù)資料
| 型號(hào)： | M30623M8T-910GP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單片16位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 42/184頁(yè) |
| 文件大小： | 1734K |
| 代理商： | M30623M8T-910GP |
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42
Tentative Specifications REV.A
S
pecifications in this manual are tentative and subject to change.
Clock Generating Circuit
Mitsubishi microcomputers
M16C / 62T Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
deveopmen
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 0006
16
). Stopping the
clock reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the X
OUT
pin
can be reduced using the X
IN
-X
OUT
drive capacity select bit (bit 5 at address 0007
16
). Reducing the drive
capacity of the X
OUT
pin reduces the power dissipation. This bit defaults to “1” when shifting to stop mode
and after a reset.
(2) Sub clock
The sub clock is generated by the sub clock oscillation circuit. No sub clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 0006
16
), the sub clock can be
selected as the BCLK by using the system clock select bit (bit 7 at address 0006
16
). However, be sure
that the sub clock oscillation has fully stabilized before switching.
After the oscillation of the sub clock oscillation circuit has stabilized, the drive capacity of the X
COUT
pin
can be reduced using the X
CIN
-X
COUT
drive capacity select bit (bit 3 at address 0006
16
). Reducing the
drive capacity of the X
COUT
pin reduces the power dissipation. This bit changes to “1” when shifting to
stop mode and at a reset.
(3) BCLK
The BCLK is the clock that drives the CPU, and is either the main clock or fc or is derived by dividing the
main clock by 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset.
When shifting to stop mode, the main clock division select bit (bit 6 at 0006
16
) is set to “1”.
(4) Peripheral function clock
f
1
, f
8
, f
32,
f
1SIO2,
f
8SIO2,
f
32SIO2
The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 0006
16
) to “1” and then executing a WAIT instruction.
f
AD
This clock has the same frequency as the main clock and is used for A-D conversion.
(5) f
C32
This clock is derived by dividing the sub clock by 32. It is used for the timer A and timer B counts.
(6) f
C
This clock has the same frequency as the sub clock. It is used for the BCLK and for the watchdog timer.
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|---|---|
| M30623M8-XXXGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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