參數(shù)資料
型號： M30600E8GP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 80/139頁
文件大?。?/td> 1782K
代理商： M30600E8GP
Mitsubishi microcomputers
M16C / 60 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
45
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Two address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter-
rupt enable flag (I flag) and processor interrupt priority level (IPL).
Figure 1.29 shows a configuration of address match interrupt-related registers.
Symbol
Address
When reset
AIER
0009 16
XXXXXX00 2
Address match interrupt enable register
Bit name
Function
Bit symbol
W
R
Address match interrup 0
enable bit
0: Interrupt disabled
1: Interrupt enabled
AIER0
Address match interrupt 1
enable bit
AIER1
Symbol
Address
When reset
RMAD0
0012 16 to 001016
X00000 16
RMAD1
0016 16 to 001416
X00000 16
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are
indeterminate.
b7
b6
b5
b4
b3
b2
b1
b0
W
R
Address setting register for address match interrupt
Function
Values that can be set
Address match interrupt register i (i = 0, 1)
0000016 to FFFFF16
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are
indeterminate.
0: Interrupt disabled
1: Interrupt enabled
b0 b7
b0
b3
(b19)
(b16)
b7
b0
(b15)
(b8)
b7
(b23)
Address Match Interrupts
Figure 1.29. Configuration of address match interrupt-related registers
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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