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M16C/28 Group
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
13. Timer S (Input Capture / Output Compare)
Rev.0.60 2004.02.01
page 124 of N
REJ09B0047-0060Z
Figures 13.2 to 13.11 show registers associated with the IC/OC base timer, the time measurement function,
and the waveform generation function.
Figure 13.2. G1BT and G1BCR0 Registers
Base timer register(Note 1)
Symbol
Address
When reset
G1BT
032116 - 032016
????16
RW
Function
(b7)
b0
Setting range
000016 to FFFF16
b8
b15
b7
(b0)
When the base timer is operating:
When read, value of the counter can be read.
When write, the counter starts counting from the
value written. When the base timer is reset, this
register is set to "000016". (Note 2)
When the base timer is reset:
This register is set to "000016" but a value read
is indeterminate. No value is written. (Note 2)
Note 1: The value which is written in this register is reflected synchronizing with the base timer count source fBT1.
Note 2: This base timer stops only when the BCK1 to BCK0 bits in the G1BCR0 register are set to "002" (count
source clock stop). This base timer operates when the BCK1 to BCK0 bits are set to other than "002".
When the BTS bit in the G1BCR1 register is set to "0", the base timer continues to be held in reset, and
remains in a no counting state with a value of "000016". When the BTS bit in the G1BCR1 register is
set to "1", this state is cleared and the timer starts counting.
Base timer control register 0
Symbol
Address
When reset
G1BCR0
032216
0000 00002
RW
Bit name
Function
Bit
symbol
: Clock stop
: Avoid this setting
: Two-phase input (Note 1)
: f1 or f2 (Note 2)
b1
0
1
b0
0
1
0
1
BCK0
BCK1
RST4
Count source
select bit
Channel 7 Input
select bit
IT
Base timer
overflow select bit
0: Bit 15 overflow
1: Bit 14 overflow
CH7INSEL
0: Base timer not reset by matching
G1BTRR
1: Base timer reset by matching
G1BTRR
Note 1: This setting can be used when the UD1 to UD0 bits in the G1BCR1 register are set to "102" (two-
phase signal processing mode). Avoid setting the BCK1 to BCK0 bits to "102" in other modes.
Note 2: When the PCLK0 bit in the PCLKR register is set to "0", the Count source is f2. And when this bit
is set to "1", the Count source is f1.
Base timer reset
cause select bit 4
0: P27/OUTC17/INPC17 pin
1: P17/INT5/INPC17/IDU pin
Reserved bit
Should be set to 0"
(b5-b3)
RW
b7
b6
b5
b4
b3
b2
b1
b0
0