![](http://datasheet.mmic.net.cn/30000/M30260M3A-XXXGP-U5_datasheet_2358673/M30260M3A-XXXGP-U5_68.png)
8. Protection
page 54
)
T
6
2
/
C
6
1
M
,
A
6
2
/
C
6
1
M
(
p
u
o
r
G
A
6
2
/
C
6
1
M
8
2
3
f
o
5
0
2
,
5
1
.
r
a
M
0
.
1
.
v
e
R
0
1
0
-
2
0
2
0
B
9
0
J
E
R
8. Protection
Note
The M16C/26T do not use the PRC3 bit in the PRCR register.
In the event that a program runs out of control, this function protects the important registers so that they will
not be rewritten easily. Figure 8.1 shows the PRCR register. The following lists the registers protected by
the PRCR register.
Registers protected by PRC0 bit: CM0, CM1, CM2, PLC0, ROCR and PCLKR registers
Registers protected by PRC1 bit: PM0, PM1, PM2, TB2SC, INVC0 and INVC1 registers
Registers protected by PRC2 bit: PD9, PACR and NDDR registers
Registers protected by PRC3 bit: VCR2 and D4INT registers
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0”
(write protected). The registers protected by the PRC2 bit should be changed in the next instruction after
setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in
which the PRC2 bit is set to “1” and the next instruction. The PRC0, PRC1 and PRC3 bits are not automati-
cally cleared to “0” by writing to any address. They can only be cleared in a program.
Protect register
Symbol
Address
After reset
PRCR
000A16
XX0000002
Bit name
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
0 : Write protected
1 : Write enabled
PRC1
PRC0
PRC2
Function
RW
Note: The PRC2 bit is set to "0" by writing to any address after setting it to "1". Other bits are not set to "0"
by writing to any address, and must therefore be set in a program.
0
RW
Nothing is assigned. When write, set to "0". When read, its
content is indeterminate.
Reserved bit
Must set to "0"
RW
Protect bit 0
Protect bit 1
Protect bit 2
Enable write to CM0, CM1, CM2,
ROCR, PLC0 and PCLKR registers
0 : Write protected
1 : Write enabled
Enable write to PM0, PM1, PM2,
TB2SC, INVC0 and INVC1
registers
0 : Write protected
1 : Write enabled
Enable write to PD9, PACR and
NDDR registers
PRC3
RW
Protect bit 3
0 : Write protected
1 : Write enabled
Enable write to VCR2 and D4INT
registers
(b5-b4)
(b7-b6)
0
Figure 8.1. PRCR Register