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參數(shù)資料
| 型號： | M30245F4-XXXGP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單片16位CMOS微機(jī) |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 99K |
| 代理商： | M30245F4-XXXGP |
1-8
Preliminary Specification
Specifications in this manual are tentative and subject to change
SFR MAP
Mitsubishi microcomputers
M30245 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.6 SFR MAP
The table below shows the peripheral control registers, their addresses, names, acronyms, and values
after reset.
Address
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
Register name
Acronym
Value after reset
Processor mode register 0
Processor mode register 1
System clock control register 0
System clock control register 1
Chip select control register
Address match interrupt enable register
Protect register
Data bank register
USB control register
PM0
PM1
CM0
CM1
CSR
AIER
PRCR
DBR
USBC
00
16
0 0
0
48
16
20
16
0 0 0 0 0 0 0 1
0 0
0 0 0
1 1 1 0
00
16
Watchdog timer start register
Watchdog timer control register
WDTS
WDC
0 0 0
00
16
00
16
Address match interrupt register 0
RMAD0
0 0 0 0
Address match interrupt register 1
RMAD1
00
16
00
16
0 0 0 0
Reserved
USB Attach/Detach register
00
16
DMA0 source pointer
SAR0
DMA0 destination pointer
DAR0
DMA0 transfer counter
TCR0
DMA0 control register
DM0CON
0 0 0 0 0 0 0
DMA1 source pointer
SAR1
DMA1 destination pointer
DAR1
DMA1 transfer counter
TCR1
DMA1 control register
DMA2 interrupt control register
DMA3 interrupt control register
USB function interrupt control register
DM1CON
DM2IC
DM3IC
USBFIC
0 0 0 0 0 0 0
0 0 0
0 0 0
0 0 0
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