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| 型號： | M30201MX-XXXFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單片16位CMOS微機(jī) |
| 文件頁數(shù)： | 146/159頁 |
| 文件大?。?/td> | 1496K |
| 代理商： | M30201MX-XXXFP |
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Unde
Appendix Standard Serial I/O Mode
Peimnay
Software commands and the status register are explained here following.
deeopmen
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
146
Standard Serial I/O Mode
The standard serial I/O mode serially inputs and outputs the software commands, addresses and data
necessary for operating (read, program, erase, etc.) the internal flash memory. It uses a purpose-specific
serial programmer.
The standard serial I/O mode differs from the parallel I/O mode in that the CPU controls operations like
rewriting (uses the CPU rewrite mode) in the flash memory or serial input for rewriting data. The standard
serial I/O mode is started by clearing the reset with V
PPH
at the CNVss pin. (For the normal microprocessor
mode, set CNVss to “L”.)
This control program is written in the boot ROM area when shipped from Mitsubishi Electric. Therefore, if
the boot ROM area is rewritten in the parallel I/O mode, the standard serial I/O mode cannot be used.
Figures DD-1 and DD-2 show the pin connections for the standard serial I/O mode. Serial data I/O uses
three UART0 pins: CLK
0
, RxD
0
, and TxD
0
and port P5
3
(BUSY).
The CLK
0
pin is the transfer clock input pin and it transfers the external transfer clock. The TxD
0
pin outputs
the CMOS signal. The P5
3
(BUSY) pin outputs an “L” level when reception setup ends and an “H” level
when the reception operation starts. Transmission and reception data is transferred serially in 8-byte
blocks.
In the standard serial I/O mode, only the user ROM area shown in Figure CC-1 can be rewritten, the boot
ROM area cannot.
The standard serial I/O mode has a 7-byte ID code. When the flash memory is not blank and the ID code
does not match the content of the flash memory, the command sent from the programmer is not accepted.
Function Overview (Standard Serial I/O Mode)
In the standard serial I/O mode, software commands, addresses and data are input and output between
the flash memory and an external device (serial programmer, etc.) using a clock synchronized serial I/O
(UART0) and P5
3
. In reception, the software commands, addresses and program data are synchronized
with the rise of the transfer clock input to the CLK
0
pin and input into the flash memory via the RxD
0
pin.
In transmission, the read data and status are synchronized with the fall of the transfer clock and output to
the outside from the TxD
0
pin.
The TxD
1
pin is CMOS output. Transmission is in 8-bit blocks and LSB first.
When busy, either during transmission or reception, or while executing an erase operation or program,
the P5
3
(BUSY) pin is “H” level. Accordingly, do not start the next transmission until the P5
3
(BUSY) pin is
“L” level.
Also, data in memory and the status register can be read after inputting a software command. It is pos-
sible to check flash memory operating status or whether a program or erase operation ended success-
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