參數(shù)資料
型號： M30201M4-XXXFP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機(jī)
文件頁數(shù)： 85/159頁
文件大小： 1496K
代理商： M30201M4-XXXFP
Unde
Clock asynchronous serial I/O (UART) mode
deeopmen
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
85
Item
Specification
Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
Start bit: 1 bit
Parity bit: Odd, even, or nothing as selected
Stop bit: 1 bit or 2 bits as selected
When internal clock is selected (bit 3 at addresses 03A0
16
, 03A8
16
= “0”) :
fi/
16
(n+1) (Note 1)
fi = f
1
, f
8
, f
32
, f
C
When external clock is selected (bit 3 at addresses 03A0
16
=“1”) :
f
EXT
/16(n+1) (Note 1) (Note 2)
To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 03A5
16
, 03AD
16
) = “1”
- Transmit buffer empty flag (bit 1 at addresses 03A5
16
, 03AD
16
) = “0”
To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 03A5
16
, 03AD
16
) = “1”
- Start bit detection
When transmitting
- Transmit interrupt cause select bits (bits 0,1 at address 03B0
16
) = “0”:
Interrupts requested when data transfer from UARTi transfer buffer register
to UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 03B0
16
) = “1”:
Interrupts requested when data transmission from UARTi transfer register is
completed
When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
Framing error
This error occurs when the number of stop bits set is not detected
Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
Sleep mode selection
This mode is used to transfer data to and from one of multiple slave micro-
computers
(2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. (See Table 1.28.) Figure 1.79 shows the UARTi transmit/receive mode register.
Table 1.28. Specifications of UART Mode
Note 1: ‘n’ denotes the value 00
16
to FF
16
that is set to the UART bit rate generator.
Note 2: f
EXT
is input from the CLK0 pin. Since UART1 does not have this pin, cannot select external clock.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to “1”.
Transfer data format
Transfer clock
Transmission start
condition
Reception start condi-
tion
Interrupt request gen-
eration timing
Error detection
Select function
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