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參數(shù)資料
| 型號： | M2V64S3DTP-7 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 64M Synchronous DRAM |
| 中文描述： | 6400同步DRAM |
| 文件頁數(shù)： | 1/51頁 |
| 文件大?。?/td> | 430K |
| 代理商： | M2V64S3DTP-7 |
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Feb.'00
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.3.2)
64M Synchronous DRAM
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x 4-BIT)
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
1
M2V64S20DTP is a 4-bank x 4,194,304-word x 4-bit,
M2V64S30DTP is a 4-bank x 2,097,152-word x 8-bit,
M2V64S40DTP is a 4-bank x 1,048,576-word x 16-bit,
synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge
of CLK. M2V64S20DTP, M2V64S30DTP and M2V64S40DTP achieve very high speed data rate up
to 133MHz for -6, and are suitable for main memory or graphic memory in computer systems.
- Single 3.3v±0.3V power supply
- Max. Clock frequency -6:133MHz<3-3-3>, -7:100MHz<2-2-2>, -8:100MHz<3-2-2>
- Fully Synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0 & BA1 (Bank Address)
- /CAS latency- 2 and 3 (programmable)
- Burst length- 1, 2, 4, 8 and full page (programmable)
- Burst type- sequential and interleave (programmable)
- Byte Control- DQML and DQMU for M2V64S40DTP
- Random column access
- Auto precharge and All bank precharge controlled by A10
- Auto refresh and Self refresh
- 4096 refresh cycles every 64ms
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
DESCRIPTION
FEATURES
PRELIMINARY
Some of contents are described for general products and are
subject to change w ithout notice.
ITEM
tCLK
tRAS
tRCD
M2V64S20/30/40DTP
-7
-8
tAC
tRC
Icc1
Icc6
Clock Cycle Time
Active to Precharge Command Period
Row to Column Delay
Access Time from CLK
Ref /Active Command Period
(Min.)
(Min.)
(Min.)
(Max.) (CL=3)
(Min.)
Operation Current
(Max.)
(Single Bank)
Self Refresh Current
(Max.)
10ns
50ns
20ns
6ns
70ns
1mA
10ns
50ns
20ns
6ns
70ns
1mA
V64S20D
V64S30D
V64S40D
-6
7.5ns
45ns
20ns
5.4ns
67.5ns
1mA
70mA
70mA
80mA
70mA
70mA
80mA
75mA
75mA
85mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M2V64S2DTP-6 | 64M Synchronous DRAM |
| M2V64S2DTP-7 | 64M Synchronous DRAM |
| M2V64S2DTP-8 | 64M Synchronous DRAM |
| M2V64S3DTP-6 | 64M Synchronous DRAM |
| M2V64S3DTP-8 | 64M Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M2V64S3DTP-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M Synchronous DRAM |
| M2V64S40BTP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M bit Synchronous DRAM |
| M2V64S40BTP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M bit Synchronous DRAM |
| M2V64S40BTP-10L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M bit Synchronous DRAM |
| M2V64S40BTP-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M bit Synchronous DRAM |
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