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參數(shù)資料
| 型號： | M28W800B100N1T |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 512K X 16 FLASH 3V PROM, 100 ns, PDSO48 |
| 封裝： | 12 X 20 MM, PLASTIC, TSOP-48 |
| 文件頁數(shù)： | 37/40頁 |
| 文件大?。?/td> | 284K |
| 代理商： | M28W800B100N1T |
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M28W800T, M28W800B
6/40
DEVICE OPERATIONS
Four control pins rule the hardware access to the
Flash memory: E, G, W, RP.
The following operations can be performed using
the appropriate bus cycles: Read, Write the Com-
mand of an Instruction, Output Disable, Standby,
Power Down (see Table 5).
Read. Read operations are used to output the
contents of the Memory Array, the Electronic Sig-
nature, the Status Register and the CFI. Both Chip
Enable (E) and Output Enable (G) must be at VIL
in order to perform the read operation. The Chip
Enable input should be used to enable the device.
Output Enable should be used to gate data onto
the output independently of the device selection.
The data read depend on the previous command
written to the memory (see instructions RD, RSIG,
RSR, RCFI and RDO). Read Array is the default
state of the device when exiting power down or af-
ter power-up.
Write. Write operations are used to give Com-
mands to the memory or to latch Input Data to be
programmed. A write operation is initiated when
Chip Enable E and Write Enable W are at VIL with
Output Enable G at VIH. Commands, Input Data
and Addresses are latched on the rising edge of W
or E, whichever occur first.
Output Disable. The data outputs are high im-
pedance when the Output Enable G is at VIH.
Standby. Standby disables most of the internal
circuitry allowing a substantial reduction of the cur-
rent consumption. The memory is in standby when
Chip Enable E is at VIH and the device is in read
mode. The power consumption is reduced to the
standby level and the outputs are set to high im-
pedance, independently from the Output Enable G
or Write Enable W inputs. If E switches to VIH dur-
ing program or erase operation, the device enters
in standby when finished.
Power Down. During power down all internal cir-
cuits are switched off, the memory is deselected
and the outputs are put in high impedance. The
memory is in Power Down when RP is at VIL. The
power consumption is reduced to the Power Down
level, independently from the Chip Enable E, Out-
put Enable G or Write Enable W inputs.
If RP is pulled to VSS during a Program or Erase,
this operation is aborted and the memory content
is no longer valid as it has been compromised by
the aborted operation.
Table 5. User Bus Operations (1)
Note: 1. X = VIL or VIH, VPPH = 12V ± 5% .
Table 6. Read Electronic Signature (RSIG Instruction)
Note: 1. RP = VIH.
Operation
E
G
W
RP
WP
VPP
DQ15-DQ0
Read
VIL
VIH
X
Don’t Care
Data Output
Write
VIL
VIH
VIL
VIH
X
VDD or VPPH
Data Input
Output Disable
VIL
VIH
X
Don’t Care
Hi-Z
Standby
VIH
XX
VIH
X
Don’t Care
Hi-Z
Power Down
X
VIL
X
Don’t Care
Hi-Z
Code
Device
E
G
W
A0
A18-A1
DQ15-DQ8
DQ7-DQ0
Manufact. Code
VIL
VIH
VIL
Don’t Care
00h
20h
Device Code
M28W800T
VIL
VIH
Don’t Care
88h
92h
M28W800B
VIL
VIH
Don’t Care
88h
93h
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