參數(shù)資料
型號： M2061-13I672.1600LF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 數(shù)字傳輸電路
英文描述： ATM/SONET/SDH SUPPORT CIRCUIT, CQCC36
封裝： 9 X 9 MM, CERAMIC, LCC-36
文件頁數(shù)： 11/12頁
文件大?。?/td> 477K
代理商： M2061-13I672.1600LF
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
8 of 12
Revised 30Jul2004
I n te g r at ed Ci rcui t Systems , In c. ● N e tw o r ki ng & Co mmun ica t io ns ● ww w. icst.co m ● tel (5 08 ) 85 2-5 4 0 0
M2060/61/62, M2065/66/67
VCSO FEC PLL FOR SONET/OTN
Preliminar y In f o r m atio n
External Loop Filter
To provide stable PLL operation, the M2060/61/62 or
M2065/66/67 requires use of an external loop filter. This
is provided via the provided filter pins (see Figure 5).
The loop filter is implemented as a differential circuit
to minimize system noise interference.
PLL bandwidth is affected by loop filter component
values, “Mfec” and “Mfin” values, and the “PLL Loop
The FEC_SEL setting can be used to actively change PLL
loop bandwidth in a given application. See “Mfec and
PLL Simulator Tool Available
for additional product information.
C
POST
C
POST
VC
nVC
R
POST
nOP_OUT
OP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
OP_IN
nOP_IN
Example Values for Loop Filter External Components 1
for Particular M206x Series Devices
VCSO Parameters: KVCO = 800kHz/V, RIN = 100k (pin NBW = 0), VCSO Bandwidth = 700kHz.
Device
Device Configuration
Example External Component Values
Nominal Performance With These Values
FRef
(MHz)
F
VCSO
(MHz)
FIN_SEL
1:0
MRSEL
1:0
R loop
C loop
R post
C post
PLL Loop
Bandwidth
Damping
Factor
Passband
Peaking (dB)
M2060
, M2060 622.08
622.08
1 1
0 1
5.6
k
10
F
68
k
470
pF
530
Hz
6.5
0.05
M2060
, M2065 155.52
669.3266
1 0
1 0 0243.0
k
0.1
F
34
k
470
pF
1k
Hz
5.9
0.06
M2061
, M2066
77.76
622.08
0 1
8.2
k
10
F
100
k
470
pF
360
Hz
6.5
0.05
M2061
19.44
622.08
0 0
1 1
8.2
k
10
F
100
k
470
pF
360
Hz
6.5
0.05
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