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參數資料
| 型號： | M2061-13-690.5692 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 數字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數： | 5/12頁 |
| 文件大?。?/td> | 477K |
| 代理商： | M2061-13-690.5692 |
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
2 of 12
Revised 30Jul2004
I n te g r at ed Ci rcui t Systems , In c. ● N e tw o r ki ng & Co mmun ica t io ns ● ww w. icst.co m ● tel (5 08 ) 85 2-5 4 0 0
M2060/61/62, M2065/66/67
VCSO FEC PLL FOR SONET/OTN
Preliminar y In f o r m atio n
PIN DESCRIPTIONS
Number
Name
I/O
Configuration
Description
1, 2, 3, 10, 14, 26
GND
Ground
Power supply ground connections.
4
9
OP_IN
nOP_IN
Input
External loop filter connections.
5
8
nOP_OUT
OP_OUT
Output
6
7
nVC
VC
Input
11, 19, 33
VCC
Power
Power supply connection, connect to +3.3V.
12
13
FOUT1
nFOUT1
Output
No internal terminator
Clock output pair 1. Differential LVPECL.
15
16
FOUT0
nFOUT0
Output
No internal terminator
Clock output pair 0. Differential LVPECL.
17
18
25
P_SEL1
P_SEL0
P_SEL2
Input
Internal pull-down resistor1
Note 1: For typical values of internal pull-down and pull-UP resistors, see
Post-PLL , P divider selection. LVCMOS/LVTTL. See Table 8,
20
nDIF_REF1
Input
Biased to Vcc/2 2
Note 2: Biased toVcc/2, with 50k
to Vcc and 50k to ground. See Differential Inputs Biased to VCC/2 on pg. 10.
Reference clock input pair 1. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
21
DIF_REF1
Internal pull-down resistor1
22
REF_SEL
Input
Internal pull-down resistor1
Reference clock input selection. LVCMOS/LVTTL:
Logic 1 selects DIF_REF1, nDIF_REF1.
Logic 0 selects DIF_REF0, nDIF_REF0.
23
nDIF_REF0
Input
Biased to Vcc/2 2
Reference clock input pair 0. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
24
DIF_REF0
Internal pull-down resistor 1
27
28
FIN_SEL1
FIN_SEL0
Input
Internal pull-down resistor1
I
nput clock frequency selection. LVCMOS/LVTTL. See
29
30
FEC_SEL0
FEC_SEL1
Input
Internal pull-down resistor1
Mfec and Rfec divider value selection. LVCMOS/ LVTTL.
31
LOL
Output
Loss of Lock indicator output. Asserted when internal PLL is
not tracking the input reference for frequency and phase. 3
Logic 1 indicates loss of lock.
Logic 0 indicates locked condition.
Note 3: See LVCMOS Output in
32
NBW
Input
Internal pull-UP resistor1
Narrow Bandwidth enable. LVCMOS/LVTTL:
Logic 1 - Narrow loop bandwidth, R
IN = 2100k
.
Logic 0 - Wide bandwidth, R
IN = 100k
.
34, 35, 36
DNC
Do Not Connect.
Internal nodes. Connection to these pins can cause erratic
device operation.
Table 2: Pin Descriptions
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